| /art/disassembler/ |
| D | disassembler_arm.cc | 85 DisassemblerStream& operator<<(const MemOperand& operand) override { in operator <<() argument
88 DCHECK(!operand.GetBaseRegister().Is(pc)); in operator <<()
89 DisassemblerStream::operator<<(operand); in operator <<()
91 if (operand.GetBaseRegister().Is(tr) && operand.IsImmediate()) { in operator <<()
93 options_->thread_offset_name_function_(os(), operand.GetOffsetImmediate()); in operator <<()
99 DisassemblerStream& operator<<(const vixl::aarch32::AlignedMemOperand& operand) override { in operator <<() argument
102 DCHECK(!operand.GetBaseRegister().Is(pc)); in operator <<()
103 return DisassemblerStream::operator<<(operand); in operator <<()
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| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.h | 86 void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
87 MacroAssembler::func_name(vixl32::DontCare, rd, rn, operand); \
111 void (func_name)(vixl32::Register rd, const vixl32::Operand& operand) { \
112 MacroAssembler::func_name(vixl32::DontCare, rd, operand); \
134 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { in Add() argument
135 if (rd.Is(rn) && operand.IsPlainRegister()) { in Add()
136 MacroAssembler::Add(rd, rn, operand); in Add()
138 MacroAssembler::Add(vixl32::DontCare, rd, rn, operand); in Add()
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| /art/test/551-checker-shifter-operand/ |
| D | info.txt | 1 Test the merging of instructions into the shifter operand on arm64.
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| /art/test/550-checker-multiply-accumulate/ |
| D | info.txt | 1 Test the merging of instructions into the shifter operand on arm64.
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| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64.h | 804 void shll(CpuRegister operand, CpuRegister shifter);
806 void shrl(CpuRegister operand, CpuRegister shifter);
808 void sarl(CpuRegister operand, CpuRegister shifter);
811 void shlq(CpuRegister operand, CpuRegister shifter);
813 void shrq(CpuRegister operand, CpuRegister shifter);
815 void sarq(CpuRegister operand, CpuRegister shifter);
875 void rorl(CpuRegister operand, CpuRegister shifter);
877 void roll(CpuRegister operand, CpuRegister shifter);
880 void rorq(CpuRegister operand, CpuRegister shifter);
882 void rolq(CpuRegister operand, CpuRegister shifter);
[all …]
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| /art/test/162-method-resolution/jasmin/ |
| D | Test5User.j | 30 dup ; Bogus operand to be swallowed by the pop in the non-exceptional path.
34 pop ; Pops the exception or the bogus operand from above.
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| /art/compiler/utils/x86/ |
| D | assembler_x86.cc | 3294 void X86Assembler::shll(Register operand, Register shifter) { in shll() argument
3295 EmitGenericShift(4, Operand(operand), shifter); in shll()
3314 void X86Assembler::shrl(Register operand, Register shifter) { in shrl() argument
3315 EmitGenericShift(5, Operand(operand), shifter); in shrl()
3334 void X86Assembler::sarl(Register operand, Register shifter) { in sarl() argument
3335 EmitGenericShift(7, Operand(operand), shifter); in sarl()
3390 void X86Assembler::roll(Register operand, Register shifter) { in roll() argument
3391 EmitGenericShift(0, Operand(operand), shifter); in roll()
3400 void X86Assembler::rorl(Register operand, Register shifter) { in rorl() argument
3401 EmitGenericShift(1, Operand(operand), shifter); in rorl()
[all …]
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| D | assembler_x86.h | 360 void rorl(Register operand, Register shifter);
362 void roll(Register operand, Register shifter);
750 void shll(Register operand, Register shifter);
754 void shrl(Register operand, Register shifter);
758 void sarl(Register operand, Register shifter);
897 void EmitOperand(int rm, const Operand& operand);
900 int rm, const Operand& operand, const Immediate& immediate, bool is_16_op = false);
905 void EmitGenericShift(int rm, const Operand& operand, const Immediate& imm);
906 void EmitGenericShift(int rm, const Operand& operand, Register shifter);
911 X86ManagedRegister operand,
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| /art/runtime/interpreter/mterp/arm/ |
| D | arithmetic.S | 25 cmp r1, #0 @ is second operand zero?
58 cmp r1, #0 @ is second operand zero?
89 cmp r1, #0 @ is second operand zero?
125 @cmp r1, #0 @ is second operand zero?
378 cmp r1, #0 @ is second operand zero?
407 cmp r1, #0 @ is second operand zero?
437 cmp r1, #0 @ is second operand zero?
467 @cmp r1, #0 @ is second operand zero?
633 cmp r1, #0 @ is second operand zero?
665 cmp r1, #0 @ is second operand zero?
[all …]
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| /art/compiler/optimizing/ |
| D | loop_optimization.cc | 87 /*out*/ HInstruction** operand);
93 /*out*/ HInstruction** operand) { in IsSignExtensionAndGet() argument
103 *operand = instruction; in IsSignExtensionAndGet()
110 *operand = instruction; in IsSignExtensionAndGet()
123 *operand = instruction; in IsSignExtensionAndGet()
139 *operand = conv; in IsSignExtensionAndGet()
146 IsZeroExtensionAndGet(instruction->InputAt(0), type, /*out*/ operand); in IsSignExtensionAndGet()
158 /*out*/ HInstruction** operand) { in IsZeroExtensionAndGet() argument
168 *operand = instruction; in IsZeroExtensionAndGet()
175 *operand = instruction; in IsZeroExtensionAndGet()
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