1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _SDE_DRM_H_ 20 #define _SDE_DRM_H_ 21 #include "drm.h" 22 #define SDE_MAX_PLANES 4 23 #define SDE_MAX_DE_CURVES 3 24 #define FILTER_EDGE_DIRECTED_2D 0x0 25 #define FILTER_CIRCULAR_2D 0x1 26 #define FILTER_SEPARABLE_1D 0x2 27 #define FILTER_BILINEAR 0x3 28 #define FILTER_ALPHA_DROP_REPEAT 0x0 29 #define FILTER_ALPHA_BILINEAR 0x1 30 #define FILTER_ALPHA_2D 0x3 31 #define FILTER_BLEND_CIRCULAR_2D 0x0 32 #define FILTER_BLEND_SEPARABLE_1D 0x1 33 #define SCALER_LUT_SWAP 0x1 34 #define SCALER_LUT_DIR_WR 0x2 35 #define SCALER_LUT_Y_CIR_WR 0x4 36 #define SCALER_LUT_UV_CIR_WR 0x8 37 #define SCALER_LUT_Y_SEP_WR 0x10 38 #define SCALER_LUT_UV_SEP_WR 0x20 39 #define SDE_DRM_BLEND_OP_NOT_DEFINED 0 40 #define SDE_DRM_BLEND_OP_OPAQUE 1 41 #define SDE_DRM_BLEND_OP_PREMULTIPLIED 2 42 #define SDE_DRM_BLEND_OP_COVERAGE 3 43 #define SDE_DRM_BLEND_OP_MAX 4 44 #define SDE_DRM_DEINTERLACE 0 45 #define SDE_DRM_BITMASK_COUNT 64 46 #define SDE_DRM_FB_NON_SEC 0 47 #define SDE_DRM_FB_SEC 1 48 #define SDE_DRM_FB_NON_SEC_DIR_TRANS 2 49 #define SDE_DRM_FB_SEC_DIR_TRANS 3 50 #define SDE_DRM_SEC_NON_SEC 0 51 #define SDE_DRM_SEC_ONLY 1 52 struct sde_drm_pix_ext_v1 { 53 int32_t num_ext_pxls_lr[SDE_MAX_PLANES]; 54 int32_t num_ext_pxls_tb[SDE_MAX_PLANES]; 55 int32_t left_ftch[SDE_MAX_PLANES]; 56 int32_t right_ftch[SDE_MAX_PLANES]; 57 int32_t top_ftch[SDE_MAX_PLANES]; 58 int32_t btm_ftch[SDE_MAX_PLANES]; 59 int32_t left_rpt[SDE_MAX_PLANES]; 60 int32_t right_rpt[SDE_MAX_PLANES]; 61 int32_t top_rpt[SDE_MAX_PLANES]; 62 int32_t btm_rpt[SDE_MAX_PLANES]; 63 }; 64 struct sde_drm_scaler_v1 { 65 struct sde_drm_pix_ext_v1 pe; 66 int32_t init_phase_x[SDE_MAX_PLANES]; 67 int32_t phase_step_x[SDE_MAX_PLANES]; 68 int32_t init_phase_y[SDE_MAX_PLANES]; 69 int32_t phase_step_y[SDE_MAX_PLANES]; 70 uint32_t horz_filter[SDE_MAX_PLANES]; 71 uint32_t vert_filter[SDE_MAX_PLANES]; 72 }; 73 struct sde_drm_de_v1 { 74 uint32_t enable; 75 int16_t sharpen_level1; 76 int16_t sharpen_level2; 77 uint16_t clip; 78 uint16_t limit; 79 uint16_t thr_quiet; 80 uint16_t thr_dieout; 81 uint16_t thr_low; 82 uint16_t thr_high; 83 uint16_t prec_shift; 84 int16_t adjust_a[SDE_MAX_DE_CURVES]; 85 int16_t adjust_b[SDE_MAX_DE_CURVES]; 86 int16_t adjust_c[SDE_MAX_DE_CURVES]; 87 }; 88 #define SDE_DYN_EXP_DISABLE 0x1 89 #define SDE_DRM_QSEED3LITE 90 #define SDE_DRM_QSEED4 91 struct sde_drm_scaler_v2 { 92 uint32_t enable; 93 uint32_t dir_en; 94 struct sde_drm_pix_ext_v1 pe; 95 uint32_t horz_decimate; 96 uint32_t vert_decimate; 97 int32_t init_phase_x[SDE_MAX_PLANES]; 98 int32_t phase_step_x[SDE_MAX_PLANES]; 99 int32_t init_phase_y[SDE_MAX_PLANES]; 100 int32_t phase_step_y[SDE_MAX_PLANES]; 101 uint32_t preload_x[SDE_MAX_PLANES]; 102 uint32_t preload_y[SDE_MAX_PLANES]; 103 uint32_t src_width[SDE_MAX_PLANES]; 104 uint32_t src_height[SDE_MAX_PLANES]; 105 uint32_t dst_width; 106 uint32_t dst_height; 107 uint32_t y_rgb_filter_cfg; 108 uint32_t uv_filter_cfg; 109 uint32_t alpha_filter_cfg; 110 uint32_t blend_cfg; 111 uint32_t lut_flag; 112 uint32_t dir_lut_idx; 113 uint32_t y_rgb_cir_lut_idx; 114 uint32_t uv_cir_lut_idx; 115 uint32_t y_rgb_sep_lut_idx; 116 uint32_t uv_sep_lut_idx; 117 struct sde_drm_de_v1 de; 118 uint32_t dir_weight; 119 uint32_t unsharp_mask_blend; 120 uint32_t de_blend; 121 uint32_t flags; 122 }; 123 #define SDE_MAX_DS_COUNT 2 124 #define SDE_DRM_DESTSCALER_ENABLE 0x1 125 #define SDE_DRM_DESTSCALER_SCALE_UPDATE 0x2 126 #define SDE_DRM_DESTSCALER_ENHANCER_UPDATE 0x4 127 #define SDE_DRM_DESTSCALER_PU_ENABLE 0x8 128 struct sde_drm_dest_scaler_cfg { 129 uint32_t flags; 130 uint32_t index; 131 uint32_t lm_width; 132 uint32_t lm_height; 133 uint64_t scaler_cfg; 134 }; 135 struct sde_drm_dest_scaler_data { 136 uint32_t num_dest_scaler; 137 struct sde_drm_dest_scaler_cfg ds_cfg[SDE_MAX_DS_COUNT]; 138 }; 139 #define SDE_CSC_MATRIX_COEFF_SIZE 9 140 #define SDE_CSC_CLAMP_SIZE 6 141 #define SDE_CSC_BIAS_SIZE 3 142 struct sde_drm_csc_v1 { 143 int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE]; 144 uint32_t pre_bias[SDE_CSC_BIAS_SIZE]; 145 uint32_t post_bias[SDE_CSC_BIAS_SIZE]; 146 uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE]; 147 uint32_t post_clamp[SDE_CSC_CLAMP_SIZE]; 148 }; 149 struct sde_drm_color { 150 uint32_t color_0; 151 uint32_t color_1; 152 uint32_t color_2; 153 uint32_t color_3; 154 }; 155 #define SDE_MAX_DIM_LAYERS 7 156 #define SDE_DRM_DIM_LAYER_INCLUSIVE 0x1 157 #define SDE_DRM_DIM_LAYER_EXCLUSIVE 0x2 158 struct sde_drm_dim_layer_cfg { 159 uint32_t flags; 160 uint32_t stage; 161 struct sde_drm_color color_fill; 162 struct drm_clip_rect rect; 163 }; 164 struct sde_drm_dim_layer_v1 { 165 uint32_t num_layers; 166 struct sde_drm_dim_layer_cfg layer_cfg[SDE_MAX_DIM_LAYERS]; 167 }; 168 #define SDE_DRM_WB_CFG 0x1 169 #define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1 << 0) 170 struct sde_drm_wb_cfg { 171 uint32_t flags; 172 uint32_t connector_id; 173 uint32_t count_modes; 174 uint64_t modes; 175 }; 176 #define SDE_MAX_ROI_V1 4 177 struct sde_drm_roi_v1 { 178 uint32_t num_rects; 179 struct drm_clip_rect roi[SDE_MAX_ROI_V1]; 180 }; 181 #define SDE_MODE_DPMS_ON 0 182 #define SDE_MODE_DPMS_LP1 1 183 #define SDE_MODE_DPMS_LP2 2 184 #define SDE_MODE_DPMS_STANDBY 3 185 #define SDE_MODE_DPMS_SUSPEND 4 186 #define SDE_MODE_DPMS_OFF 5 187 #define SDE_RECOVERY_SUCCESS 0 188 #define SDE_RECOVERY_CAPTURE 1 189 #define SDE_RECOVERY_HARD_RESET 2 190 #endif 191