1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _MSM_NPU_H_ 20 #define _MSM_NPU_H_ 21 #include <linux/types.h> 22 #define MSM_NPU_IOCTL_MAGIC 'n' 23 #define MSM_NPU_GET_INFO _IOWR(MSM_NPU_IOCTL_MAGIC, 1, struct msm_npu_get_info_ioctl) 24 #define MSM_NPU_MAP_BUF _IOWR(MSM_NPU_IOCTL_MAGIC, 2, struct msm_npu_map_buf_ioctl) 25 #define MSM_NPU_UNMAP_BUF _IOWR(MSM_NPU_IOCTL_MAGIC, 3, struct msm_npu_unmap_buf_ioctl) 26 #define MSM_NPU_LOAD_NETWORK _IOWR(MSM_NPU_IOCTL_MAGIC, 4, struct msm_npu_load_network_ioctl) 27 #define MSM_NPU_UNLOAD_NETWORK _IOWR(MSM_NPU_IOCTL_MAGIC, 5, struct msm_npu_unload_network_ioctl) 28 #define MSM_NPU_EXEC_NETWORK _IOWR(MSM_NPU_IOCTL_MAGIC, 6, struct msm_npu_exec_network_ioctl) 29 #define MSM_NPU_LOAD_NETWORK_V2 _IOWR(MSM_NPU_IOCTL_MAGIC, 7, struct msm_npu_load_network_ioctl_v2) 30 #define MSM_NPU_EXEC_NETWORK_V2 _IOWR(MSM_NPU_IOCTL_MAGIC, 8, struct msm_npu_exec_network_ioctl_v2) 31 #define MSM_NPU_RECEIVE_EVENT _IOR(MSM_NPU_IOCTL_MAGIC, 9, struct msm_npu_event) 32 #define MSM_NPU_SET_PROP _IOW(MSM_NPU_IOCTL_MAGIC, 10, struct msm_npu_property) 33 #define MSM_NPU_GET_PROP _IOW(MSM_NPU_IOCTL_MAGIC, 11, struct msm_npu_property) 34 #define MSM_NPU_EVENT_TYPE_START 0x10000000 35 #define MSM_NPU_EVENT_TYPE_EXEC_DONE (MSM_NPU_EVENT_TYPE_START + 1) 36 #define MSM_NPU_EVENT_TYPE_EXEC_V2_DONE (MSM_NPU_EVENT_TYPE_START + 2) 37 #define MSM_NPU_EVENT_TYPE_SSR (MSM_NPU_EVENT_TYPE_START + 3) 38 #define MSM_NPU_MAX_INPUT_LAYER_NUM 8 39 #define MSM_NPU_MAX_OUTPUT_LAYER_NUM 4 40 #define MSM_NPU_MAX_PATCH_LAYER_NUM (MSM_NPU_MAX_INPUT_LAYER_NUM + MSM_NPU_MAX_OUTPUT_LAYER_NUM) 41 #define MSM_NPU_PROP_ID_START 0x100 42 #define MSM_NPU_PROP_ID_FW_STATE (MSM_NPU_PROP_ID_START + 0) 43 #define MSM_NPU_PROP_ID_PERF_MODE (MSM_NPU_PROP_ID_START + 1) 44 #define MSM_NPU_PROP_ID_PERF_MODE_MAX (MSM_NPU_PROP_ID_START + 2) 45 #define MSM_NPU_PROP_ID_DRV_VERSION (MSM_NPU_PROP_ID_START + 3) 46 #define MSM_NPU_PROP_ID_HARDWARE_VERSION (MSM_NPU_PROP_ID_START + 4) 47 #define MSM_NPU_PROP_ID_IPC_QUEUE_INFO (MSM_NPU_PROP_ID_START + 5) 48 #define MSM_NPU_PROP_ID_DRV_FEATURE (MSM_NPU_PROP_ID_START + 6) 49 #define MSM_NPU_FW_PROP_ID_START 0x1000 50 #define MSM_NPU_PROP_ID_DCVS_MODE (MSM_NPU_FW_PROP_ID_START + 0) 51 #define MSM_NPU_PROP_ID_DCVS_MODE_MAX (MSM_NPU_FW_PROP_ID_START + 1) 52 #define MSM_NPU_PROP_ID_CLK_GATING_MODE (MSM_NPU_FW_PROP_ID_START + 2) 53 #define MSM_NPU_PROP_ID_HW_VERSION (MSM_NPU_FW_PROP_ID_START + 3) 54 #define MSM_NPU_PROP_ID_FW_VERSION (MSM_NPU_FW_PROP_ID_START + 4) 55 #define MSM_NPU_FEATURE_MULTI_EXECUTE 0x1 56 #define MSM_NPU_FEATURE_ASYNC_EXECUTE 0x2 57 #define PROP_PARAM_MAX_SIZE 8 58 struct msm_npu_patch_info { 59 uint32_t chunk_id; 60 uint16_t instruction_size_in_bytes; 61 uint16_t variable_size_in_bits; 62 uint16_t shift_value_in_bits; 63 uint32_t loc_offset; 64 }; 65 struct msm_npu_layer { 66 uint32_t layer_id; 67 struct msm_npu_patch_info patch_info; 68 int32_t buf_hdl; 69 uint32_t buf_size; 70 uint64_t buf_phys_addr; 71 }; 72 struct msm_npu_patch_info_v2 { 73 uint32_t value; 74 uint32_t chunk_id; 75 uint32_t instruction_size_in_bytes; 76 uint32_t variable_size_in_bits; 77 uint32_t shift_value_in_bits; 78 uint32_t loc_offset; 79 }; 80 struct msm_npu_patch_buf_info { 81 uint64_t buf_phys_addr; 82 uint32_t buf_id; 83 }; 84 struct msm_npu_map_buf_ioctl { 85 int32_t buf_ion_hdl; 86 uint32_t size; 87 uint64_t npu_phys_addr; 88 }; 89 struct msm_npu_unmap_buf_ioctl { 90 int32_t buf_ion_hdl; 91 uint64_t npu_phys_addr; 92 }; 93 struct msm_npu_get_info_ioctl { 94 uint32_t firmware_version; 95 uint32_t flags; 96 }; 97 struct msm_npu_load_network_ioctl { 98 int32_t buf_ion_hdl; 99 uint64_t buf_phys_addr; 100 uint32_t buf_size; 101 uint32_t first_block_size; 102 uint32_t flags; 103 uint32_t network_hdl; 104 uint32_t priority; 105 uint32_t perf_mode; 106 }; 107 struct msm_npu_load_network_ioctl_v2 { 108 uint64_t buf_phys_addr; 109 uint64_t patch_info; 110 int32_t buf_ion_hdl; 111 uint32_t buf_size; 112 uint32_t first_block_size; 113 uint32_t flags; 114 uint32_t network_hdl; 115 uint32_t priority; 116 uint32_t perf_mode; 117 uint32_t num_layers; 118 uint32_t patch_info_num; 119 uint32_t reserved; 120 }; 121 struct msm_npu_unload_network_ioctl { 122 uint32_t network_hdl; 123 }; 124 struct msm_npu_exec_network_ioctl { 125 uint32_t network_hdl; 126 uint32_t input_layer_num; 127 struct msm_npu_layer input_layers[MSM_NPU_MAX_INPUT_LAYER_NUM]; 128 uint32_t output_layer_num; 129 struct msm_npu_layer output_layers[MSM_NPU_MAX_OUTPUT_LAYER_NUM]; 130 uint32_t patching_required; 131 uint32_t async; 132 uint32_t flags; 133 }; 134 struct msm_npu_exec_network_ioctl_v2 { 135 uint64_t stats_buf_addr; 136 uint64_t patch_buf_info; 137 uint32_t network_hdl; 138 uint32_t async; 139 uint32_t flags; 140 uint32_t stats_buf_size; 141 uint32_t patch_buf_info_num; 142 uint32_t reserved; 143 }; 144 struct msm_npu_event_execute_done { 145 uint32_t network_hdl; 146 int32_t exec_result; 147 }; 148 struct msm_npu_event_execute_v2_done { 149 uint32_t network_hdl; 150 int32_t exec_result; 151 uint32_t stats_buf_size; 152 }; 153 struct msm_npu_event_ssr { 154 uint32_t network_hdl; 155 }; 156 struct msm_npu_event { 157 uint32_t type; 158 union { 159 struct msm_npu_event_execute_done exec_done; 160 struct msm_npu_event_execute_v2_done exec_v2_done; 161 struct msm_npu_event_ssr ssr; 162 uint8_t data[128]; 163 } u; 164 uint32_t reserved[4]; 165 }; 166 struct msm_npu_property { 167 uint32_t prop_id; 168 uint32_t num_of_params; 169 uint32_t network_hdl; 170 uint32_t prop_param[PROP_PARAM_MAX_SIZE]; 171 }; 172 #endif 173