1 #ifndef __UAPI_MSMB_ISP__ 2 #define __UAPI_MSMB_ISP__ 3 4 #include <linux/videodev2.h> 5 #include <media/msmb_camera.h> 6 7 #define MAX_PLANES_PER_STREAM 3 8 #define MAX_NUM_STREAM 7 9 10 #define ISP_VERSION_48 48 11 #define ISP_VERSION_47 47 12 #define ISP_VERSION_46 46 13 #define ISP_VERSION_44 44 14 #define ISP_VERSION_40 40 15 #define ISP_VERSION_32 32 16 #define ISP_NATIVE_BUF_BIT (0x10000 << 0) 17 #define ISP0_BIT (0x10000 << 1) 18 #define ISP1_BIT (0x10000 << 2) 19 #define ISP_META_CHANNEL_BIT (0x10000 << 3) 20 #define ISP_SCRATCH_BUF_BIT (0x10000 << 4) 21 #define ISP_OFFLINE_STATS_BIT (0x10000 << 5) 22 #define ISP_SVHDR_IN_BIT (0x10000 << 6) /* RDI hw stream for SVHDR */ 23 #define ISP_SVHDR_OUT_BIT (0x10000 << 7) /* SVHDR output bufq stream*/ 24 25 #define ISP_STATS_STREAM_BIT 0x80000000 26 27 #define VFE_HW_LIMIT 1 28 29 struct msm_vfe_cfg_cmd_list; 30 31 enum ISP_START_PIXEL_PATTERN { 32 ISP_BAYER_RGRGRG, 33 ISP_BAYER_GRGRGR, 34 ISP_BAYER_BGBGBG, 35 ISP_BAYER_GBGBGB, 36 ISP_YUV_YCbYCr, 37 ISP_YUV_YCrYCb, 38 ISP_YUV_CbYCrY, 39 ISP_YUV_CrYCbY, 40 ISP_PIX_PATTERN_MAX 41 }; 42 43 enum msm_vfe_plane_fmt { 44 Y_PLANE, 45 CB_PLANE, 46 CR_PLANE, 47 CRCB_PLANE, 48 CBCR_PLANE, 49 VFE_PLANE_FMT_MAX 50 }; 51 52 enum msm_vfe_input_src { 53 VFE_PIX_0, 54 VFE_RAW_0, 55 VFE_RAW_1, 56 VFE_RAW_2, 57 VFE_SRC_MAX, 58 }; 59 60 enum msm_vfe_axi_stream_src { 61 PIX_ENCODER, 62 PIX_VIEWFINDER, 63 PIX_VIDEO, 64 CAMIF_RAW, 65 IDEAL_RAW, 66 RDI_INTF_0, 67 RDI_INTF_1, 68 RDI_INTF_2, 69 VFE_AXI_SRC_MAX 70 }; 71 72 enum msm_vfe_frame_skip_pattern { 73 NO_SKIP, 74 EVERY_2FRAME, 75 EVERY_3FRAME, 76 EVERY_4FRAME, 77 EVERY_5FRAME, 78 EVERY_6FRAME, 79 EVERY_7FRAME, 80 EVERY_8FRAME, 81 EVERY_16FRAME, 82 EVERY_32FRAME, 83 SKIP_ALL, 84 SKIP_RANGE, 85 MAX_SKIP, 86 }; 87 88 /* 89 * Define an unused period. When this period is set it means that the stream is 90 * stopped(i.e the pattern is 0). We don't track the current pattern, just the 91 * period defines what the pattern is, if period is this then pattern is 0 else 92 * pattern is 1 93 */ 94 #define MSM_VFE_STREAM_STOP_PERIOD 15 95 96 enum msm_isp_stats_type { 97 MSM_ISP_STATS_AEC, /* legacy based AEC */ 98 MSM_ISP_STATS_AF, /* legacy based AF */ 99 MSM_ISP_STATS_AWB, /* legacy based AWB */ 100 MSM_ISP_STATS_RS, /* legacy based RS */ 101 MSM_ISP_STATS_CS, /* legacy based CS */ 102 MSM_ISP_STATS_IHIST, /* legacy based HIST */ 103 MSM_ISP_STATS_SKIN, /* legacy based SKIN */ 104 MSM_ISP_STATS_BG, /* Bayer Grids */ 105 MSM_ISP_STATS_BF, /* Bayer Focus */ 106 MSM_ISP_STATS_BE, /* Bayer Exposure*/ 107 MSM_ISP_STATS_BHIST, /* Bayer Hist */ 108 MSM_ISP_STATS_BF_SCALE, /* Bayer Focus scale */ 109 MSM_ISP_STATS_HDR_BE, /* HDR Bayer Exposure */ 110 MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */ 111 MSM_ISP_STATS_AEC_BG, /* AEC BG */ 112 MSM_ISP_STATS_MAX /* MAX */ 113 }; 114 115 /* 116 * @stats_type_mask: Stats type mask (enum msm_isp_stats_type). 117 * @stream_src_mask: Stream src mask (enum msm_vfe_axi_stream_src) 118 * @skip_mode: skip pattern, if skip mode is range only then min/max is used 119 * @min_frame_id: minimum frame id (valid only if skip_mode = RANGE) 120 * @max_frame_id: maximum frame id (valid only if skip_mode = RANGE) 121 */ 122 struct msm_isp_sw_framskip { 123 uint32_t stats_type_mask; 124 uint32_t stream_src_mask; 125 enum msm_vfe_frame_skip_pattern skip_mode; 126 uint32_t min_frame_id; 127 uint32_t max_frame_id; 128 }; 129 130 enum msm_vfe_testgen_color_pattern { 131 COLOR_BAR_8_COLOR, 132 UNICOLOR_WHITE, 133 UNICOLOR_YELLOW, 134 UNICOLOR_CYAN, 135 UNICOLOR_GREEN, 136 UNICOLOR_MAGENTA, 137 UNICOLOR_RED, 138 UNICOLOR_BLUE, 139 UNICOLOR_BLACK, 140 MAX_COLOR, 141 }; 142 143 enum msm_vfe_camif_input { 144 CAMIF_DISABLED, 145 CAMIF_PAD_REG_INPUT, 146 CAMIF_MIDDI_INPUT, 147 CAMIF_MIPI_INPUT, 148 }; 149 150 struct msm_vfe_fetch_engine_cfg { 151 uint32_t input_format; 152 uint32_t buf_width; 153 uint32_t buf_height; 154 uint32_t fetch_width; 155 uint32_t fetch_height; 156 uint32_t x_offset; 157 uint32_t y_offset; 158 uint32_t buf_stride; 159 }; 160 161 enum msm_vfe_camif_output_format { 162 CAMIF_QCOM_RAW, 163 CAMIF_MIPI_RAW, 164 CAMIF_PLAIN_8, 165 CAMIF_PLAIN_16, 166 CAMIF_MAX_FORMAT, 167 }; 168 169 /* 170 * Camif output general configuration 171 */ 172 struct msm_vfe_camif_subsample_cfg { 173 uint32_t irq_subsample_period; 174 uint32_t irq_subsample_pattern; 175 uint32_t sof_counter_step; 176 uint32_t pixel_skip; 177 uint32_t line_skip; 178 uint32_t first_line; 179 uint32_t last_line; 180 uint32_t first_pixel; 181 uint32_t last_pixel; 182 enum msm_vfe_camif_output_format output_format; 183 }; 184 185 /* 186 * Camif frame and window configuration 187 */ 188 struct msm_vfe_camif_cfg { 189 uint32_t lines_per_frame; 190 uint32_t pixels_per_line; 191 uint32_t first_pixel; 192 uint32_t last_pixel; 193 uint32_t first_line; 194 uint32_t last_line; 195 uint32_t epoch_line0; 196 uint32_t epoch_line1; 197 uint32_t is_split; 198 enum msm_vfe_camif_input camif_input; 199 struct msm_vfe_camif_subsample_cfg subsample_cfg; 200 }; 201 202 struct msm_vfe_testgen_cfg { 203 uint32_t lines_per_frame; 204 uint32_t pixels_per_line; 205 uint32_t v_blank; 206 uint32_t h_blank; 207 enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern; 208 uint32_t rotate_period; 209 enum msm_vfe_testgen_color_pattern color_bar_pattern; 210 uint32_t burst_num_frame; 211 }; 212 213 enum msm_vfe_inputmux { 214 CAMIF, 215 TESTGEN, 216 EXTERNAL_READ, 217 }; 218 219 enum msm_vfe_stats_composite_group { 220 STATS_COMPOSITE_GRP_NONE, 221 STATS_COMPOSITE_GRP_1, 222 STATS_COMPOSITE_GRP_2, 223 STATS_COMPOSITE_GRP_MAX, 224 }; 225 226 enum msm_vfe_hvx_streaming_cmd { 227 HVX_DISABLE, 228 HVX_ONE_WAY, 229 HVX_ROUND_TRIP 230 }; 231 232 struct msm_vfe_pix_cfg { 233 struct msm_vfe_camif_cfg camif_cfg; 234 struct msm_vfe_testgen_cfg testgen_cfg; 235 struct msm_vfe_fetch_engine_cfg fetch_engine_cfg; 236 enum msm_vfe_inputmux input_mux; 237 enum ISP_START_PIXEL_PATTERN pixel_pattern; 238 uint32_t input_format; 239 enum msm_vfe_hvx_streaming_cmd hvx_cmd; 240 uint32_t is_split; 241 }; 242 243 struct msm_vfe_rdi_cfg { 244 uint8_t cid; 245 uint8_t frame_based; 246 }; 247 248 struct msm_vfe_input_cfg { 249 union { 250 struct msm_vfe_pix_cfg pix_cfg; 251 struct msm_vfe_rdi_cfg rdi_cfg; 252 } d; 253 enum msm_vfe_input_src input_src; 254 uint32_t input_pix_clk; 255 }; 256 257 struct msm_vfe_fetch_eng_start { 258 uint32_t session_id; 259 uint32_t stream_id; 260 uint32_t buf_idx; 261 uint8_t offline_mode; 262 uint32_t fd; 263 uint32_t buf_addr; 264 uint32_t frame_id; 265 }; 266 267 enum msm_vfe_fetch_eng_pass { 268 OFFLINE_FIRST_PASS, 269 OFFLINE_SECOND_PASS, 270 OFFLINE_MAX_PASS, 271 }; 272 273 struct msm_vfe_fetch_eng_multi_pass_start { 274 uint32_t session_id; 275 uint32_t stream_id; 276 uint32_t buf_idx; 277 uint8_t offline_mode; 278 uint32_t fd; 279 uint32_t buf_addr; 280 uint32_t frame_id; 281 uint32_t output_buf_idx; 282 uint32_t input_buf_offset; 283 enum msm_vfe_fetch_eng_pass offline_pass; 284 uint32_t output_stream_id; 285 }; 286 287 struct msm_vfe_axi_plane_cfg { 288 uint32_t output_width; /*Include padding*/ 289 uint32_t output_height; 290 uint32_t output_stride; 291 uint32_t output_scan_lines; 292 uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/ 293 uint32_t plane_addr_offset; 294 uint8_t csid_src; /*RDI 0-2*/ 295 uint8_t rdi_cid;/*CID 1-16*/ 296 }; 297 298 enum msm_stream_rdi_input_type { 299 MSM_CAMERA_RDI_MIN, 300 MSM_CAMERA_RDI_PDAF, 301 MSM_CAMERA_RDI_MAX, 302 }; 303 304 struct msm_vfe_axi_stream_request_cmd { 305 uint32_t session_id; 306 uint32_t stream_id; 307 uint32_t vt_enable; 308 uint32_t output_format;/*Planar/RAW/Misc*/ 309 enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/ 310 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 311 312 uint32_t burst_count; 313 uint32_t hfr_mode; 314 uint8_t frame_base; 315 316 uint32_t init_frame_drop; /*MAX 31 Frames*/ 317 enum msm_vfe_frame_skip_pattern frame_skip_pattern; 318 uint8_t buf_divert; /* if TRUE no vb2 buf done. */ 319 /*Return values*/ 320 uint32_t axi_stream_handle; 321 uint32_t controllable_output; 322 uint32_t burst_len; 323 /* Flag indicating memory input stream */ 324 enum msm_stream_rdi_input_type rdi_input_type; 325 }; 326 327 struct msm_vfe_axi_stream_release_cmd { 328 uint32_t stream_handle; 329 }; 330 331 enum msm_vfe_axi_stream_cmd { 332 STOP_STREAM, 333 START_STREAM, 334 STOP_IMMEDIATELY, 335 }; 336 337 struct msm_vfe_axi_stream_cfg_cmd { 338 uint8_t num_streams; 339 uint32_t stream_handle[VFE_AXI_SRC_MAX]; 340 enum msm_vfe_axi_stream_cmd cmd; 341 uint8_t sync_frame_id_src; 342 }; 343 344 enum msm_vfe_axi_stream_update_type { 345 ENABLE_STREAM_BUF_DIVERT, 346 DISABLE_STREAM_BUF_DIVERT, 347 UPDATE_STREAM_FRAMEDROP_PATTERN, 348 UPDATE_STREAM_STATS_FRAMEDROP_PATTERN, 349 UPDATE_STREAM_AXI_CONFIG, 350 UPDATE_STREAM_REQUEST_FRAMES, 351 UPDATE_STREAM_ADD_BUFQ, 352 UPDATE_STREAM_REMOVE_BUFQ, 353 UPDATE_STREAM_SW_FRAME_DROP, 354 UPDATE_STREAM_REQUEST_FRAMES_VER2, 355 UPDATE_STREAM_OFFLINE_AXI_CONFIG, 356 }; 357 #define UPDATE_STREAM_REQUEST_FRAMES_VER2 UPDATE_STREAM_REQUEST_FRAMES_VER2 358 359 enum msm_vfe_iommu_type { 360 IOMMU_ATTACH, 361 IOMMU_DETACH, 362 }; 363 364 enum msm_vfe_buff_queue_id { 365 VFE_BUF_QUEUE_DEFAULT, 366 VFE_BUF_QUEUE_SHARED, 367 VFE_BUF_QUEUE_MAX, 368 }; 369 370 struct msm_vfe_axi_stream_cfg_update_info { 371 uint32_t stream_handle; 372 uint32_t output_format; 373 uint32_t user_stream_id; 374 uint32_t frame_id; 375 enum msm_vfe_frame_skip_pattern skip_pattern; 376 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 377 struct msm_isp_sw_framskip sw_skip_info; 378 }; 379 380 struct msm_vfe_axi_stream_cfg_update_info_req_frm { 381 uint32_t stream_handle; 382 uint32_t user_stream_id; 383 uint32_t frame_id; 384 uint32_t buf_index; 385 }; 386 387 struct msm_vfe_axi_halt_cmd { 388 uint32_t stop_camif; 389 uint32_t overflow_detected; 390 uint32_t blocking_halt; 391 }; 392 393 struct msm_vfe_axi_reset_cmd { 394 uint32_t blocking; 395 uint32_t frame_id; 396 }; 397 398 struct msm_vfe_axi_restart_cmd { 399 uint32_t enable_camif; 400 }; 401 402 struct msm_vfe_axi_stream_update_cmd { 403 uint32_t num_streams; 404 enum msm_vfe_axi_stream_update_type update_type; 405 /* 406 * For backward compatibility, ensure 1st member of any struct 407 * in union below is uint32_t stream_handle. 408 */ 409 union { 410 struct msm_vfe_axi_stream_cfg_update_info 411 update_info[MSM_ISP_STATS_MAX]; 412 struct msm_vfe_axi_stream_cfg_update_info_req_frm req_frm_ver2; 413 }; 414 }; 415 416 struct msm_vfe_smmu_attach_cmd { 417 uint32_t security_mode; 418 uint32_t iommu_attach_mode; 419 }; 420 421 struct msm_vfe_stats_stream_request_cmd { 422 uint32_t session_id; 423 uint32_t stream_id; 424 enum msm_isp_stats_type stats_type; 425 uint32_t composite_flag; 426 uint32_t framedrop_pattern; 427 uint32_t init_frame_drop; /*MAX 31 Frames*/ 428 uint32_t irq_subsample_pattern; 429 uint32_t buffer_offset; 430 uint32_t stream_handle; 431 }; 432 433 struct msm_vfe_stats_stream_release_cmd { 434 uint32_t stream_handle; 435 }; 436 struct msm_vfe_stats_stream_cfg_cmd { 437 uint8_t num_streams; 438 uint32_t stream_handle[MSM_ISP_STATS_MAX]; 439 uint8_t enable; 440 uint32_t stats_burst_len; 441 }; 442 443 enum msm_vfe_reg_cfg_type { 444 VFE_WRITE, 445 VFE_WRITE_MB, 446 VFE_READ, 447 VFE_CFG_MASK, 448 VFE_WRITE_DMI_16BIT, 449 VFE_WRITE_DMI_32BIT, 450 VFE_WRITE_DMI_64BIT, 451 VFE_READ_DMI_16BIT, 452 VFE_READ_DMI_32BIT, 453 VFE_READ_DMI_64BIT, 454 GET_MAX_CLK_RATE, 455 GET_CLK_RATES, 456 GET_ISP_ID, 457 VFE_HW_UPDATE_LOCK, 458 VFE_HW_UPDATE_UNLOCK, 459 SET_WM_UB_SIZE, 460 SET_UB_POLICY, 461 GET_VFE_HW_LIMIT, 462 }; 463 464 struct msm_vfe_cfg_cmd2 { 465 uint16_t num_cfg; 466 uint16_t cmd_len; 467 void *cfg_data; 468 void *cfg_cmd; 469 }; 470 471 struct msm_vfe_cfg_cmd_list { 472 struct msm_vfe_cfg_cmd2 cfg_cmd; 473 struct msm_vfe_cfg_cmd_list *next; 474 uint32_t next_size; 475 }; 476 477 struct msm_vfe_reg_rw_info { 478 uint32_t reg_offset; 479 uint32_t cmd_data_offset; 480 uint32_t len; 481 }; 482 483 struct msm_vfe_reg_mask_info { 484 uint32_t reg_offset; 485 uint32_t mask; 486 uint32_t val; 487 }; 488 489 struct msm_vfe_reg_dmi_info { 490 uint32_t hi_tbl_offset; /*Optional*/ 491 uint32_t lo_tbl_offset; /*Required*/ 492 uint32_t len; 493 }; 494 495 struct msm_vfe_reg_cfg_cmd { 496 union { 497 struct msm_vfe_reg_rw_info rw_info; 498 struct msm_vfe_reg_mask_info mask_info; 499 struct msm_vfe_reg_dmi_info dmi_info; 500 } u; 501 502 enum msm_vfe_reg_cfg_type cmd_type; 503 }; 504 505 enum vfe_sd_type { 506 VFE_SD_0 = 0, 507 VFE_SD_1, 508 VFE_SD_COMMON, 509 VFE_SD_MAX, 510 }; 511 512 /* When you change the value below, check for the sof event_data size. 513 * V4l2 limits payload to 64 bytes 514 */ 515 #define MS_NUM_SLAVE_MAX 1 516 517 /* Usecases when 2 HW need to be related or synced */ 518 enum msm_vfe_dual_hw_type { 519 DUAL_NONE = 0, 520 DUAL_HW_VFE_SPLIT = 1, 521 DUAL_HW_MASTER_SLAVE = 2, 522 }; 523 524 /* Type for 2 INTF when used in Master-Slave mode */ 525 enum msm_vfe_dual_hw_ms_type { 526 MS_TYPE_NONE, 527 MS_TYPE_MASTER, 528 MS_TYPE_SLAVE, 529 }; 530 531 struct msm_isp_set_dual_hw_ms_cmd { 532 uint8_t num_src; 533 /* Each session can be only one type but multiple intf if YUV cam */ 534 enum msm_vfe_dual_hw_ms_type dual_hw_ms_type; 535 /* Primary intf is mostly associated with preview. 536 * This primary intf SOF frame_id and timestamp is tracked 537 * and used to calculate delta 538 */ 539 enum msm_vfe_input_src primary_intf; 540 /* input_src array indicates other input INTF that may be Master/Slave. 541 * For these additional intf, frame_id and timestamp are not saved. 542 * However, if these are slaves then they will still get their 543 * frame_id from Master 544 */ 545 enum msm_vfe_input_src input_src[VFE_SRC_MAX]; 546 uint32_t sof_delta_threshold; /* In milliseconds. Sent for Master */ 547 }; 548 549 enum msm_isp_buf_type { 550 ISP_PRIVATE_BUF, 551 ISP_SHARE_BUF, 552 MAX_ISP_BUF_TYPE, 553 }; 554 555 struct msm_isp_unmap_buf_req { 556 uint32_t fd; 557 }; 558 559 struct msm_isp_buf_request { 560 uint32_t session_id; 561 uint32_t stream_id; 562 uint8_t num_buf; 563 uint32_t handle; 564 enum msm_isp_buf_type buf_type; 565 }; 566 567 struct msm_isp_buf_request_ver2 { 568 uint32_t session_id; 569 uint32_t stream_id; 570 uint8_t num_buf; 571 uint32_t handle; 572 enum msm_isp_buf_type buf_type; 573 enum smmu_attach_mode security_mode; 574 uint32_t reserved[4]; 575 }; 576 577 struct msm_isp_qbuf_plane { 578 uint32_t addr; 579 uint32_t offset; 580 uint32_t length; 581 }; 582 583 struct msm_isp_qbuf_buffer { 584 struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM]; 585 uint32_t num_planes; 586 }; 587 588 struct msm_isp_qbuf_info { 589 uint32_t handle; 590 int32_t buf_idx; 591 /*Only used for prepare buffer*/ 592 struct msm_isp_qbuf_buffer buffer; 593 /*Only used for diverted buffer*/ 594 uint32_t dirty_buf; 595 }; 596 597 struct msm_isp_clk_rates { 598 uint32_t svs_rate; 599 uint32_t nominal_rate; 600 uint32_t high_rate; 601 }; 602 603 struct msm_vfe_axi_src_state { 604 enum msm_vfe_input_src input_src; 605 uint32_t src_active; 606 uint32_t src_frame_id; 607 }; 608 609 enum msm_isp_event_mask_index { 610 ISP_EVENT_MASK_INDEX_STATS_NOTIFY = 0, 611 ISP_EVENT_MASK_INDEX_ERROR = 1, 612 ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT = 2, 613 ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE = 3, 614 ISP_EVENT_MASK_INDEX_REG_UPDATE = 4, 615 ISP_EVENT_MASK_INDEX_SOF = 5, 616 ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6, 617 ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7, 618 ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8, 619 ISP_EVENT_MASK_INDEX_BUF_DONE = 9, 620 ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING = 10, 621 ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH = 11, 622 ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR = 12, 623 }; 624 625 626 #define ISP_EVENT_SUBS_MASK_NONE 0 627 628 #define ISP_EVENT_SUBS_MASK_STATS_NOTIFY \ 629 (1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY) 630 631 #define ISP_EVENT_SUBS_MASK_ERROR \ 632 (1 << ISP_EVENT_MASK_INDEX_ERROR) 633 634 #define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT \ 635 (1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT) 636 637 #define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE \ 638 (1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE) 639 640 #define ISP_EVENT_SUBS_MASK_REG_UPDATE \ 641 (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE) 642 643 #define ISP_EVENT_SUBS_MASK_SOF \ 644 (1 << ISP_EVENT_MASK_INDEX_SOF) 645 646 #define ISP_EVENT_SUBS_MASK_BUF_DIVERT \ 647 (1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT) 648 649 #define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY \ 650 (1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY) 651 652 #define ISP_EVENT_SUBS_MASK_FE_READ_DONE \ 653 (1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE) 654 655 #define ISP_EVENT_SUBS_MASK_BUF_DONE \ 656 (1 << ISP_EVENT_MASK_INDEX_BUF_DONE) 657 658 #define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING \ 659 (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING) 660 661 #define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH \ 662 (1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH) 663 664 #define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR \ 665 (1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR) 666 667 enum msm_isp_event_idx { 668 ISP_REG_UPDATE = 0, 669 ISP_EPOCH_0 = 1, 670 ISP_EPOCH_1 = 2, 671 ISP_START_ACK = 3, 672 ISP_STOP_ACK = 4, 673 ISP_IRQ_VIOLATION = 5, 674 ISP_STATS_OVERFLOW = 6, 675 ISP_BUF_DONE = 7, 676 ISP_FE_RD_DONE = 8, 677 ISP_IOMMU_P_FAULT = 9, 678 ISP_ERROR = 10, 679 ISP_HW_FATAL_ERROR = 11, 680 ISP_PING_PONG_MISMATCH = 12, 681 ISP_REG_UPDATE_MISSING = 13, 682 ISP_BUF_FATAL_ERROR = 14, 683 ISP_EVENT_MAX = 15 684 }; 685 686 #define ISP_EVENT_OFFSET 8 687 #define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) 688 #define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) 689 #define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) 690 #define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET)) 691 #define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET)) 692 #define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) 693 #define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0) 694 #define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1) 695 #define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) 696 #define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) 697 #define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) 698 #define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) 699 #define ISP_EVENT_ERROR (ISP_EVENT_BASE + ISP_ERROR) 700 #define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE) 701 #define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1) 702 #define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE) 703 #define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) 704 #define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) 705 #define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) 706 #define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE) 707 #define ISP_EVENT_IOMMU_P_FAULT (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT) 708 #define ISP_EVENT_HW_FATAL_ERROR (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR) 709 #define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH) 710 #define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING) 711 #define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR) 712 #define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE) 713 714 /* The msm_v4l2_event_data structure should match the 715 * v4l2_event.u.data field. 716 * should not exceed 64 bytes 717 */ 718 719 struct msm_isp_buf_event { 720 uint32_t session_id; 721 uint32_t stream_id; 722 uint32_t handle; 723 uint32_t output_format; 724 int8_t buf_idx; 725 }; 726 struct msm_isp_fetch_eng_event { 727 uint32_t session_id; 728 uint32_t stream_id; 729 uint32_t handle; 730 uint32_t fd; 731 int8_t buf_idx; 732 int8_t offline_mode; 733 }; 734 struct msm_isp_stats_event { 735 uint32_t stats_mask; /* 4 bytes */ 736 uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */ 737 uint8_t pd_stats_idx; 738 }; 739 740 struct msm_isp_stream_ack { 741 uint32_t session_id; 742 uint32_t stream_id; 743 uint32_t handle; 744 }; 745 746 enum msm_vfe_error_type { 747 ISP_ERROR_NONE, 748 ISP_ERROR_CAMIF, 749 ISP_ERROR_BUS_OVERFLOW, 750 ISP_ERROR_RETURN_EMPTY_BUFFER, 751 ISP_ERROR_FRAME_ID_MISMATCH, 752 ISP_ERROR_MAX, 753 }; 754 755 struct msm_isp_error_info { 756 enum msm_vfe_error_type err_type; 757 uint32_t session_id; 758 uint32_t stream_id; 759 uint32_t stream_id_mask; 760 }; 761 762 /* This structure reports delta between master and slave */ 763 struct msm_isp_ms_delta_info { 764 uint8_t num_delta_info; 765 uint32_t delta[MS_NUM_SLAVE_MAX]; 766 }; 767 768 /* This is sent in EPOCH irq */ 769 struct msm_isp_output_info { 770 uint8_t regs_not_updated; 771 /* mask with bufq_handle for regs not updated or return empty */ 772 uint16_t output_err_mask; 773 /* mask with stream_idx for get_buf failed */ 774 uint8_t stream_framedrop_mask; 775 /* mask with stats stream_idx for get_buf failed */ 776 uint16_t stats_framedrop_mask; 777 /* delta between master and slave */ 778 }; 779 780 /* This structure is piggybacked with SOF event */ 781 struct msm_isp_sof_info { 782 uint8_t regs_not_updated; 783 /* mask with bufq_handle for regs not updated */ 784 uint16_t reg_update_fail_mask; 785 /* mask with bufq_handle for get_buf failed */ 786 uint32_t stream_get_buf_fail_mask; 787 /* mask with stats stream_idx for get_buf failed */ 788 uint16_t stats_get_buf_fail_mask; 789 /* delta between master and slave */ 790 struct msm_isp_ms_delta_info ms_delta_info; 791 /* 792 * mask with AXI_SRC in paused state. In PAUSED 793 * state there is no Buffer output. So this mask is used 794 * to report drop. 795 */ 796 uint16_t axi_updating_mask; 797 /* extended mask with bufq_handle for regs not updated */ 798 uint32_t reg_update_fail_mask_ext; 799 }; 800 #define AXI_UPDATING_MASK 1 801 #define REG_UPDATE_FAIL_MASK_EXT 1 802 803 struct msm_isp_event_data { 804 /*Wall clock except for buffer divert events 805 *which use monotonic clock 806 */ 807 struct timeval timestamp; 808 /* Monotonic timestamp since bootup */ 809 struct timeval mono_timestamp; 810 uint32_t frame_id; 811 union { 812 /* Sent for Stats_Done event */ 813 struct msm_isp_stats_event stats; 814 /* Sent for Buf_Divert event */ 815 struct msm_isp_buf_event buf_done; 816 /* Sent for offline fetch done event */ 817 struct msm_isp_fetch_eng_event fetch_done; 818 /* Sent for Error_Event */ 819 struct msm_isp_error_info error_info; 820 /* 821 * This struct needs to be removed once 822 * userspace switches to sof_info 823 */ 824 struct msm_isp_output_info output_info; 825 /* Sent for SOF event */ 826 struct msm_isp_sof_info sof_info; 827 } u; /* union can have max 52 bytes */ 828 }; 829 830 enum msm_vfe_ahb_clk_vote { 831 MSM_ISP_CAMERA_AHB_SVS_VOTE = 1, 832 MSM_ISP_CAMERA_AHB_TURBO_VOTE = 2, 833 MSM_ISP_CAMERA_AHB_NOMINAL_VOTE = 3, 834 MSM_ISP_CAMERA_AHB_SUSPEND_VOTE = 4, 835 }; 836 837 struct msm_isp_ahb_clk_cfg { 838 uint32_t vote; 839 uint32_t reserved[2]; 840 }; 841 842 enum msm_vfe_dual_cam_sync_mode { 843 MSM_ISP_DUAL_CAM_ASYNC, 844 MSM_ISP_DUAL_CAM_SYNC, 845 }; 846 847 struct msm_isp_dual_hw_master_slave_sync { 848 uint32_t sync_mode; 849 uint32_t reserved[2]; 850 }; 851 852 struct msm_vfe_dual_lpm_mode { 853 enum msm_vfe_axi_stream_src stream_src[VFE_AXI_SRC_MAX]; 854 uint32_t num_src; 855 uint32_t lpm_mode; 856 }; 857 #define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') 858 #define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') 859 #define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') 860 #define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') 861 #define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') 862 #define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') 863 #define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') 864 #define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') 865 #define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') 866 #define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') 867 #define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') 868 #define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') 869 #define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4') 870 #define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4') 871 #define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4') 872 #define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4') 873 #define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0') 874 #define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0') 875 #define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0') 876 #define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0') 877 #define V4L2_PIX_FMT_P16BGGR12 v4l2_fourcc('P', 'B', 'G', '2') 878 #define V4L2_PIX_FMT_P16GBRG12 v4l2_fourcc('P', 'G', 'B', '2') 879 #define V4L2_PIX_FMT_P16GRBG12 v4l2_fourcc('P', 'G', 'R', '2') 880 #define V4L2_PIX_FMT_P16RGGB12 v4l2_fourcc('P', 'R', 'G', '2') 881 #define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4') 882 #define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1') 883 #define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T') 884 #define V4L2_PIX_FMT_META10 v4l2_fourcc('Q', 'M', '1', '0') 885 #define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.GRGR.*/ 886 #define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.RGRG.*/ 887 #define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') /* 14 GRGR.BGBG.*/ 888 #define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.GBGB.*/ 889 890 enum msm_isp_ioctl_cmd_code { 891 MSM_VFE_REG_CFG = BASE_VIDIOC_PRIVATE, 892 MSM_ISP_REQUEST_BUF, 893 MSM_ISP_ENQUEUE_BUF, 894 MSM_ISP_RELEASE_BUF, 895 MSM_ISP_REQUEST_STREAM, 896 MSM_ISP_CFG_STREAM, 897 MSM_ISP_RELEASE_STREAM, 898 MSM_ISP_INPUT_CFG, 899 MSM_ISP_SET_SRC_STATE, 900 MSM_ISP_REQUEST_STATS_STREAM, 901 MSM_ISP_CFG_STATS_STREAM, 902 MSM_ISP_RELEASE_STATS_STREAM, 903 MSM_ISP_REG_UPDATE_CMD, 904 MSM_ISP_UPDATE_STREAM, 905 MSM_VFE_REG_LIST_CFG, 906 MSM_ISP_SMMU_ATTACH, 907 MSM_ISP_UPDATE_STATS_STREAM, 908 MSM_ISP_AXI_HALT, 909 MSM_ISP_AXI_RESET, 910 MSM_ISP_AXI_RESTART, 911 MSM_ISP_FETCH_ENG_START, 912 MSM_ISP_DEQUEUE_BUF, 913 MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, 914 MSM_ISP_MAP_BUF_START_FE, 915 MSM_ISP_UNMAP_BUF, 916 MSM_ISP_AHB_CLK_CFG, 917 MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, 918 MSM_ISP_FETCH_ENG_MULTI_PASS_START, 919 MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, 920 MSM_ISP_REQUEST_BUF_VER2, 921 MSM_ISP_DUAL_HW_LPM_MODE, 922 }; 923 924 #define VIDIOC_MSM_VFE_REG_CFG \ 925 _IOWR('V', MSM_VFE_REG_CFG, \ 926 struct msm_vfe_cfg_cmd2) 927 928 #define VIDIOC_MSM_ISP_REQUEST_BUF \ 929 _IOWR('V', MSM_ISP_REQUEST_BUF, \ 930 struct msm_isp_buf_request) 931 932 #define VIDIOC_MSM_ISP_ENQUEUE_BUF \ 933 _IOWR('V', MSM_ISP_ENQUEUE_BUF, \ 934 struct msm_isp_qbuf_info) 935 936 #define VIDIOC_MSM_ISP_RELEASE_BUF \ 937 _IOWR('V', MSM_ISP_RELEASE_BUF, \ 938 struct msm_isp_buf_request) 939 940 #define VIDIOC_MSM_ISP_REQUEST_STREAM \ 941 _IOWR('V', MSM_ISP_REQUEST_STREAM, \ 942 struct msm_vfe_axi_stream_request_cmd) 943 944 #define VIDIOC_MSM_ISP_CFG_STREAM \ 945 _IOWR('V', MSM_ISP_CFG_STREAM, \ 946 struct msm_vfe_axi_stream_cfg_cmd) 947 948 #define VIDIOC_MSM_ISP_RELEASE_STREAM \ 949 _IOWR('V', MSM_ISP_RELEASE_STREAM, \ 950 struct msm_vfe_axi_stream_release_cmd) 951 952 #define VIDIOC_MSM_ISP_INPUT_CFG \ 953 _IOWR('V', MSM_ISP_INPUT_CFG, \ 954 struct msm_vfe_input_cfg) 955 956 #define VIDIOC_MSM_ISP_SET_SRC_STATE \ 957 _IOWR('V', MSM_ISP_SET_SRC_STATE, \ 958 struct msm_vfe_axi_src_state) 959 960 #define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \ 961 _IOWR('V', MSM_ISP_REQUEST_STATS_STREAM, \ 962 struct msm_vfe_stats_stream_request_cmd) 963 964 #define VIDIOC_MSM_ISP_CFG_STATS_STREAM \ 965 _IOWR('V', MSM_ISP_CFG_STATS_STREAM, \ 966 struct msm_vfe_stats_stream_cfg_cmd) 967 968 #define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \ 969 _IOWR('V', MSM_ISP_RELEASE_STATS_STREAM, \ 970 struct msm_vfe_stats_stream_release_cmd) 971 972 #define VIDIOC_MSM_ISP_REG_UPDATE_CMD \ 973 _IOWR('V', MSM_ISP_REG_UPDATE_CMD, \ 974 enum msm_vfe_input_src) 975 976 #define VIDIOC_MSM_ISP_UPDATE_STREAM \ 977 _IOWR('V', MSM_ISP_UPDATE_STREAM, \ 978 struct msm_vfe_axi_stream_update_cmd) 979 980 #define VIDIOC_MSM_VFE_REG_LIST_CFG \ 981 _IOWR('V', MSM_VFE_REG_LIST_CFG, \ 982 struct msm_vfe_cfg_cmd_list) 983 984 #define VIDIOC_MSM_ISP_SMMU_ATTACH \ 985 _IOWR('V', MSM_ISP_SMMU_ATTACH, \ 986 struct msm_vfe_smmu_attach_cmd) 987 988 #define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \ 989 _IOWR('V', MSM_ISP_UPDATE_STATS_STREAM, \ 990 struct msm_vfe_axi_stream_update_cmd) 991 992 #define VIDIOC_MSM_ISP_AXI_HALT \ 993 _IOWR('V', MSM_ISP_AXI_HALT, \ 994 struct msm_vfe_axi_halt_cmd) 995 996 #define VIDIOC_MSM_ISP_AXI_RESET \ 997 _IOWR('V', MSM_ISP_AXI_RESET, \ 998 struct msm_vfe_axi_reset_cmd) 999 1000 #define VIDIOC_MSM_ISP_AXI_RESTART \ 1001 _IOWR('V', MSM_ISP_AXI_RESTART, \ 1002 struct msm_vfe_axi_restart_cmd) 1003 1004 #define VIDIOC_MSM_ISP_FETCH_ENG_START \ 1005 _IOWR('V', MSM_ISP_FETCH_ENG_START, \ 1006 struct msm_vfe_fetch_eng_start) 1007 1008 #define VIDIOC_MSM_ISP_DEQUEUE_BUF \ 1009 _IOWR('V', MSM_ISP_DEQUEUE_BUF, \ 1010 struct msm_isp_qbuf_info) 1011 1012 #define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE \ 1013 _IOWR('V', MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, \ 1014 struct msm_isp_set_dual_hw_ms_cmd) 1015 1016 #define VIDIOC_MSM_ISP_MAP_BUF_START_FE \ 1017 _IOWR('V', MSM_ISP_MAP_BUF_START_FE, \ 1018 struct msm_vfe_fetch_eng_start) 1019 1020 #define VIDIOC_MSM_ISP_UNMAP_BUF \ 1021 _IOWR('V', MSM_ISP_UNMAP_BUF, \ 1022 struct msm_isp_unmap_buf_req) 1023 1024 #define VIDIOC_MSM_ISP_AHB_CLK_CFG \ 1025 _IOWR('V', MSM_ISP_AHB_CLK_CFG, struct msm_isp_ahb_clk_cfg) 1026 1027 #define VIDIOC_MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC \ 1028 _IOWR('V', MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, \ 1029 struct msm_isp_dual_hw_master_slave_sync) 1030 1031 #define VIDIOC_MSM_ISP_FETCH_ENG_MULTI_PASS_START \ 1032 _IOWR('V', MSM_ISP_FETCH_ENG_MULTI_PASS_START, \ 1033 struct msm_vfe_fetch_eng_multi_pass_start) 1034 1035 #define VIDIOC_MSM_ISP_MAP_BUF_START_MULTI_PASS_FE \ 1036 _IOWR('V', MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, \ 1037 struct msm_vfe_fetch_eng_multi_pass_start) 1038 1039 #define VIDIOC_MSM_ISP_REQUEST_BUF_VER2 \ 1040 _IOWR('V', MSM_ISP_REQUEST_BUF_VER2, struct msm_isp_buf_request_ver2) 1041 1042 #define VIDIOC_MSM_ISP_DUAL_HW_LPM_MODE \ 1043 _IOWR('V', MSM_ISP_DUAL_HW_LPM_MODE, \ 1044 struct msm_vfe_dual_lpm_mode) 1045 1046 #endif /* __MSMB_ISP__ */ 1047