1MPP configuration
2-----------------
3Multi-Purpose Ports (MPP) are configurable through platform PCDs.
4In order to set desired pin multiplexing, .dsc file needs to be modified.
5(OpenPlatformPkg/Platforms/Marvell/Armada/{platform_name}.dsc - please refer to
6Documentation/Build.txt for currently supported {platftorm_name} )
7Following PCDs are available:
8
9 gMarvellTokenSpaceGuid.PcdMppChipCount
10
11Indicates how many different chips are placed on board. So far up to 4 chips
12are supported.
13
14Every MPP PCD has <Num> part where
15 <Num> stands for chip ID (order is not important, but configuration will be
16 set for first PcdMppChipCount chips).
17
18Below is example for the first chip (Chip0).
19
20 gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag
21
22Indicates that register order is reversed. (Needs to be used only for AP806-Z1)
23
24 gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress
25
26This is base address for MPP configuration register.
27
28 gMarvellTokenSpaceGuid.PcdChip0MppPinCount
29
30Defines how many MPP pins are available.
31
32 gMarvellTokenSpaceGuid.PcdChip0MppSel0
33 gMarvellTokenSpaceGuid.PcdChip0MppSel1
34 gMarvellTokenSpaceGuid.PcdChip0MppSel2
35
36This registers defines functions of 10 pins in ascending order.
37
38Examples
39--------
40#APN806-A0 MPP SET
41 gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
42 gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
43 gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3
44 gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 }
45 gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
46
47Set pin 6 and 7 to 0xa function:
48 gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 }
49