1 /** @file
2
3 ACPI Memory mapped configuration space base address Description Table (MCFG).
4 Implementation based on PCI Firmware Specification Revision 3.0 final draft,
5 downloadable at http://www.pcisig.com/home
6
7 Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
8
9 This program and the accompanying materials are licensed and
10 made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the
12 license may be found at http://opensource.org/licenses/bsd-license.php
13
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16
17 **/
18
19 #include <AmdStyxAcpiLib.h>
20
21 //
22 // CSRT for ARM_CCN504 (L3 CACHE)
23 //
24 #define AMD_ACPI_ARM_CCN504_CSRT_REVISION 0
25 #define AMD_ACPI_ARM_CCN504_VENDOR_ID SIGNATURE_32('A','R','M','H')
26 #define AMD_ACPI_ARM_CCN504_DEVICE_ID 0x510
27 #define AMD_ACPI_ARM_CCN504_RESOURCE_TYPE 0x04
28 #define AMD_ACPI_ARM_CCN504_DESC_VERSION 1
29 #define AMD_ACPI_ARM_CCN504_HNF_COUNT 8
30 #define AMD_ACPI_ARM_CCN504_BASE_ADDR 0xE8000000ULL
31 #define AMD_ACPI_ARM_CCN504_CACHE_SIZE 0x00800000ULL
32
33 //
34 // Ensure proper (byte-packed) structure formats
35 //
36 #pragma pack(push, 1)
37
38 typedef struct {
39 UINT32 Version;
40 UINT8 HnfRegionCount;
41 UINT8 Reserved[3];
42 UINT64 BaseAddress;
43 UINT64 CacheSize;
44 } AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR;
45
46 typedef struct {
47 UINT32 Length;
48 UINT16 ResourceType;
49 UINT16 ResourceSubtype;
50 UINT32 UID;
51 AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR Ccn504Desc;
52 } AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR;
53
54 typedef struct {
55 UINT32 Length;
56 UINT32 VendorId;
57 UINT32 SubvendorId;
58 UINT16 DeviceId;
59 UINT16 SubdeviceId;
60 UINT16 Revision;
61 UINT8 Reserved[2];
62 UINT32 SharedInfoLength;
63 AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR RsrcDesc;
64 } AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP;
65
66 typedef struct {
67 EFI_ACPI_DESCRIPTION_HEADER Header;
68 AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP RsrcGroup;
69 } AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE;
70
71
72 AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE AcpiCsrt = {
73 AMD_ACPI_HEADER (EFI_ACPI_5_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE,
74 AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE,
75 AMD_ACPI_ARM_CCN504_CSRT_REVISION),
76 { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP), // UINT32 RsrcGroup.Length
77 AMD_ACPI_ARM_CCN504_VENDOR_ID, // UINT32 RsrcGroup.VendorId
78 0, // UINT32 RsrcGroup.SubvendorId
79 AMD_ACPI_ARM_CCN504_DEVICE_ID, // UINT16 RsrcGroup.DeviceId
80 0, // UINT16 RsrcGroup.SubdeviceId
81 0, // UINT16 RsrcGroup.Revision
82 { 0 }, // UINT8 RsrcGroup.Reserved[]
83 0, // UINT32 RsrcGroup.SharedInfoLength
84 { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR), // UINT32 RsrcDesc.Length
85 AMD_ACPI_ARM_CCN504_RESOURCE_TYPE, // UINT16 RsrcDesc.ResourceType
86 0, // UINT16 RsrcDesc.ResourceSubtype
87 0, // UINT32 RsrcDesc.UID
88 { AMD_ACPI_ARM_CCN504_DESC_VERSION, // UINT32 Ccn504Desc.Version
89 AMD_ACPI_ARM_CCN504_HNF_COUNT, // UINT8 Ccn504Desc.HnfRegionCount
90 { 0 }, // UINT8 Ccn504Desc.Reserved[]
91 AMD_ACPI_ARM_CCN504_BASE_ADDR, // UINT64 Ccn504Desc.BaseAddress
92 AMD_ACPI_ARM_CCN504_CACHE_SIZE, // UINT64 Ccn504Desc.CacheSize
93 },
94 },
95 },
96 };
97
98 #pragma pack(pop)
99
100
101 EFI_ACPI_DESCRIPTION_HEADER *
CsrtHeader(VOID)102 CsrtHeader (
103 VOID
104 )
105 {
106 return &AcpiCsrt.Header;
107 }
108