1 /********************************************************************************
2 Copyright (C) 2016 Marvell International Ltd.
3
4 Marvell BSD License Option
5
6 If you received this File from Marvell, you may opt to use, redistribute and/or
7 modify this File under the following licensing terms.
8 Redistribution and use in source and binary forms, with or without modification,
9 are permitted provided that the following conditions are met:
10
11 * Redistributions of source code must retain the above copyright notice,
12 this list of conditions and the following disclaimer.
13
14 * Redistributions in binary form must reproduce the above copyright
15 notice, this list of conditions and the following disclaimer in the
16 documentation and/or other materials provided with the distribution.
17
18 * Neither the name of Marvell nor the names of its contributors may be
19 used to endorse or promote products derived from this software without
20 specific prior written permission.
21
22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
23 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
26 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
31 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32
33 *******************************************************************************/
34
35 #include <Library/ArmLib.h>
36 #include <Library/ArmPlatformLib.h>
37 #include <Library/DebugLib.h>
38 #include <Library/PcdLib.h>
39 #include <Library/MemoryAllocationLib.h>
40 #include <Library/IoLib.h>
41
42 #define MPP_PIN_VAL(pin,func) (((func) & 0xf) << ((pin) * 4))
43 #define MPP_MAX_REGS 8
44 #define MPP_PINS_PER_REG 8
45 #define PCD_PINS_PER_GROUP 10
46
47 #define SD_MMC_PHY_AP_MPP_OFFSET 0x100
48 #define SD_MMC_PHY_CP0_MPP_OFFSET 0x424
49 #define MPP_ON_SDPHY_ENABLE (1 << 0)
50
51 #define MAX_CHIPS 4
52
53 #define GET_PCD_PTR(id,num) PcdGetPtr(PcdChip##id##MppSel##num)
54 #define GET_PIN_COUNT(id) PcdGet32(PcdChip##id##MppPinCount)
55 #define GET_BASE(id) PcdGet64(PcdChip##id##MppBaseAddress)
56 #define GET_REV_FLAG(id) PcdGetBool(PcdChip##id##MppReverseFlag)
57
58 /* We get chip number */
59 #define GetMppPcd(id) { \
60 PinCount[id] = GET_PIN_COUNT(id); \
61 MppRegPcd[id][7] = GET_PCD_PTR(id,7); \
62 MppRegPcd[id][6] = GET_PCD_PTR(id,6); \
63 MppRegPcd[id][5] = GET_PCD_PTR(id,5); \
64 MppRegPcd[id][4] = GET_PCD_PTR(id,4); \
65 MppRegPcd[id][3] = GET_PCD_PTR(id,3); \
66 MppRegPcd[id][2] = GET_PCD_PTR(id,2); \
67 MppRegPcd[id][1] = GET_PCD_PTR(id,1); \
68 MppRegPcd[id][0] = GET_PCD_PTR(id,0); \
69 BaseAddr[id] = GET_BASE(id); \
70 ReverseFlag[id] = GET_REV_FLAG(id); \
71 }
72
73 STATIC
74 VOID
SetRegisterValue(UINT8 RegCount,UINT8 ** MppRegPcd,UINTN BaseAddr,BOOLEAN ReverseFlag)75 SetRegisterValue (
76 UINT8 RegCount,
77 UINT8 **MppRegPcd,
78 UINTN BaseAddr,
79 BOOLEAN ReverseFlag
80 )
81 {
82 UINT32 i, j, CtrlVal;
83 INTN Sign;
84
85 Sign = ReverseFlag ? -1 : 1;
86
87 for (i = 0; i < RegCount; i++) {
88 CtrlVal = 0;
89 for (j = 0; j < MPP_PINS_PER_REG; j++) {
90 CtrlVal |= MPP_PIN_VAL(7 * (UINTN) ReverseFlag + j * Sign,
91 MppRegPcd[i][7 * (UINTN) ReverseFlag + j * Sign]);
92 }
93 MmioWrite32 (BaseAddr + 4 * i * Sign, CtrlVal);
94 }
95 }
96
97 STATIC
98 /* Transform PCD MPP group format into hardware register format */
99 UINT8
PcdToMppRegs(UINTN PinCount,UINT8 ** MppRegPcd)100 PcdToMppRegs (
101 UINTN PinCount,
102 UINT8 **MppRegPcd
103 )
104 {
105 UINT8 MppRegPcdTmp[MPP_MAX_REGS][MPP_PINS_PER_REG];
106 UINT8 PcdGroupCount, MppRegCount;
107 UINTN i, j, k, l;
108
109 if (PinCount == 0) {
110 return 0;
111 }
112
113 PcdGroupCount = PinCount / PCD_PINS_PER_GROUP;
114 if ((PinCount % PCD_PINS_PER_GROUP) != 0) {
115 PcdGroupCount += 1;
116 }
117
118 MppRegCount = PinCount / MPP_PINS_PER_REG;
119 if ((PinCount % MPP_PINS_PER_REG) != 0) {
120 MppRegCount += 1;
121 }
122
123 /* Fill temporary table with data from PCD groups in HW format */
124 for (i = 0; i < PcdGroupCount; i++) {
125 for (j = 0; j < PCD_PINS_PER_GROUP; j++) {
126 k = (PCD_PINS_PER_GROUP * i + j) / MPP_PINS_PER_REG;
127 l = (PCD_PINS_PER_GROUP * i + j) % MPP_PINS_PER_REG;
128 MppRegPcdTmp[k][l] = MppRegPcd[i][j];
129 }
130 }
131
132 /* Update input table */
133 for (i = 0; i < MppRegCount; i++) {
134 for (j = 0; j < MPP_PINS_PER_REG; j++) {
135 MppRegPcd[i][j] = MppRegPcdTmp[i][j];
136 }
137 }
138
139 return MppRegCount;
140 }
141
142 STATIC
143 VOID
SetSdMmcPhyMpp(UINTN BaseAddr,UINT32 Index)144 SetSdMmcPhyMpp (
145 UINTN BaseAddr,
146 UINT32 Index
147 )
148 {
149 UINTN Size, Offset;
150 UINT8 *Ptr;
151 UINT32 Reg;
152
153 Size = PcdGetSize(PcdPciESdhci);
154 Ptr = (UINT8 *) PcdGetPtr(PcdPciESdhci);
155
156 if (Ptr == NULL || Index >= Size) {
157 return;
158 }
159
160 /* Check if SDHCI controller is enabled on the HW block */
161 if (Ptr[Index] != 1) {
162 return;
163 }
164
165 /* Choose adequate Offset */
166 switch (Index) {
167 case 0:
168 Offset = SD_MMC_PHY_AP_MPP_OFFSET;
169 break;
170 case 1:
171 Offset = SD_MMC_PHY_CP0_MPP_OFFSET;
172 break;
173 default:
174 return;
175 }
176
177 /*
178 * If there is SDHCI controller on platform, connect SD/MMC PHY to
179 * SD/MMC controller insted of using it as MPP multiplexer
180 */
181 Reg = MmioRead32 (BaseAddr + Offset);
182 Reg &= ~MPP_ON_SDPHY_ENABLE;
183 MmioWrite32 (BaseAddr + Offset, Reg);
184 }
185
186 EFI_STATUS
MppInitialize()187 MppInitialize (
188 )
189 {
190 UINTN BaseAddr[MAX_CHIPS], PinCount[MAX_CHIPS], RegCount;
191 BOOLEAN ReverseFlag[MAX_CHIPS];
192 UINT8 *MppRegPcd[MAX_CHIPS][MPP_MAX_REGS];
193 UINT32 i, ChipCount;
194
195 ChipCount = PcdGet32 (PcdMppChipCount);
196
197 /* Read all needed PCD for MPP configuration */
198 GetMppPcd(0);
199 GetMppPcd(1);
200 GetMppPcd(2);
201 GetMppPcd(3);
202
203 for (i = 0; i < MAX_CHIPS; i++) {
204 if (i == ChipCount)
205 break;
206 RegCount = PcdToMppRegs (PinCount[i], MppRegPcd[i]);
207 SetRegisterValue (RegCount, MppRegPcd[i], BaseAddr[i], ReverseFlag[i]);
208
209 /*
210 * eMMC PHY IP has its own MPP configuration.
211 */
212 SetSdMmcPhyMpp (BaseAddr[i], i);
213 }
214
215 return EFI_SUCCESS;
216 }
217