1/*
2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <bl_common.h>
10
11
12	.globl	bl2_entrypoint
13
14
15
16func bl2_entrypoint
17	/*---------------------------------------------
18	 * Save from x1 the extents of the tzram
19	 * available to BL2 for future use.
20	 * x0 is not currently used.
21	 * ---------------------------------------------
22	 */
23	mov	x20, x1
24
25	/* ---------------------------------------------
26	 * Set the exception vector to something sane.
27	 * ---------------------------------------------
28	 */
29	adr	x0, early_exceptions
30	msr	vbar_el1, x0
31	isb
32
33	/* ---------------------------------------------
34	 * Enable the SError interrupt now that the
35	 * exception vectors have been setup.
36	 * ---------------------------------------------
37	 */
38	msr	daifclr, #DAIF_ABT_BIT
39
40	/* ---------------------------------------------
41	 * Enable the instruction cache, stack pointer
42	 * and data access alignment checks
43	 * ---------------------------------------------
44	 */
45	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
46	mrs	x0, sctlr_el1
47	orr	x0, x0, x1
48	msr	sctlr_el1, x0
49	isb
50
51	/* ---------------------------------------------
52	 * Invalidate the RW memory used by the BL2
53	 * image. This includes the data and NOBITS
54	 * sections. This is done to safeguard against
55	 * possible corruption of this memory by dirty
56	 * cache lines in a system cache as a result of
57	 * use by an earlier boot loader stage.
58	 * ---------------------------------------------
59	 */
60	adr	x0, __RW_START__
61	adr	x1, __RW_END__
62	sub	x1, x1, x0
63	bl	inv_dcache_range
64
65	/* ---------------------------------------------
66	 * Zero out NOBITS sections. There are 2 of them:
67	 *   - the .bss section;
68	 *   - the coherent memory section.
69	 * ---------------------------------------------
70	 */
71	ldr	x0, =__BSS_START__
72	ldr	x1, =__BSS_SIZE__
73	bl	zeromem
74
75#if USE_COHERENT_MEM
76	ldr	x0, =__COHERENT_RAM_START__
77	ldr	x1, =__COHERENT_RAM_UNALIGNED_SIZE__
78	bl	zeromem
79#endif
80
81	/* --------------------------------------------
82	 * Allocate a stack whose memory will be marked
83	 * as Normal-IS-WBWA when the MMU is enabled.
84	 * There is no risk of reading stale stack
85	 * memory after enabling the MMU as only the
86	 * primary cpu is running at the moment.
87	 * --------------------------------------------
88	 */
89	bl	plat_set_my_stack
90
91	/* ---------------------------------------------
92	 * Initialize the stack protector canary before
93	 * any C code is called.
94	 * ---------------------------------------------
95	 */
96#if STACK_PROTECTOR_ENABLED
97	bl	update_stack_protector_canary
98#endif
99
100	/* ---------------------------------------------
101	 * Perform early platform setup & platform
102	 * specific early arch. setup e.g. mmu setup
103	 * ---------------------------------------------
104	 */
105	mov	x0, x20
106	bl	bl2_early_platform_setup
107	bl	bl2_plat_arch_setup
108
109	/* ---------------------------------------------
110	 * Jump to main function.
111	 * ---------------------------------------------
112	 */
113	bl	bl2_main
114
115	/* ---------------------------------------------
116	 * Should never reach this point.
117	 * ---------------------------------------------
118	 */
119	no_ret	plat_panic_handler
120
121endfunc bl2_entrypoint
122