1/*
2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <platform_def.h>
8
9OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
10OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
11ENTRY(bl2u_entrypoint)
12
13MEMORY {
14    RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
15}
16
17
18SECTIONS
19{
20    . = BL2U_BASE;
21    ASSERT(. == ALIGN(4096),
22           "BL2U_BASE address is not aligned on a page boundary.")
23
24#if SEPARATE_CODE_AND_RODATA
25    .text . : {
26        __TEXT_START__ = .;
27        *bl2u_entrypoint.o(.text*)
28        *(.text*)
29        *(.vectors)
30        . = NEXT(4096);
31        __TEXT_END__ = .;
32     } >RAM
33
34    .rodata . : {
35        __RODATA_START__ = .;
36        *(.rodata*)
37        . = NEXT(4096);
38        __RODATA_END__ = .;
39    } >RAM
40#else
41    ro . : {
42        __RO_START__ = .;
43        *bl2u_entrypoint.o(.text*)
44        *(.text*)
45        *(.rodata*)
46
47        *(.vectors)
48        __RO_END_UNALIGNED__ = .;
49        /*
50         * Memory page(s) mapped to this section will be marked as
51         * read-only, executable.  No RW data from the next section must
52         * creep in.  Ensure the rest of the current memory page is unused.
53         */
54        . = NEXT(4096);
55        __RO_END__ = .;
56    } >RAM
57#endif
58
59    /*
60     * Define a linker symbol to mark start of the RW memory area for this
61     * image.
62     */
63    __RW_START__ = . ;
64
65    /*
66     * .data must be placed at a lower address than the stacks if the stack
67     * protector is enabled. Alternatively, the .data.stack_protector_canary
68     * section can be placed independently of the main .data section.
69     */
70    .data . : {
71        __DATA_START__ = .;
72        *(.data*)
73        __DATA_END__ = .;
74    } >RAM
75
76    stacks (NOLOAD) : {
77        __STACKS_START__ = .;
78        *(tzfw_normal_stacks)
79        __STACKS_END__ = .;
80    } >RAM
81
82    /*
83     * The .bss section gets initialised to 0 at runtime.
84     * Its base address should be 16-byte aligned for better performance of the
85     * zero-initialization code.
86     */
87    .bss : ALIGN(16) {
88        __BSS_START__ = .;
89        *(SORT_BY_ALIGNMENT(.bss*))
90        *(COMMON)
91        __BSS_END__ = .;
92    } >RAM
93
94    /*
95     * The xlat_table section is for full, aligned page tables (4K).
96     * Removing them from .bss avoids forcing 4K alignment on
97     * the .bss section and eliminates the unecessary zero init
98     */
99    xlat_table (NOLOAD) : {
100        *(xlat_table)
101    } >RAM
102
103#if USE_COHERENT_MEM
104    /*
105     * The base address of the coherent memory section must be page-aligned (4K)
106     * to guarantee that the coherent data are stored on their own pages and
107     * are not mixed with normal data.  This is required to set up the correct
108     * memory attributes for the coherent data page tables.
109     */
110    coherent_ram (NOLOAD) : ALIGN(4096) {
111        __COHERENT_RAM_START__ = .;
112        *(tzfw_coherent_mem)
113        __COHERENT_RAM_END_UNALIGNED__ = .;
114        /*
115         * Memory page(s) mapped to this section will be marked
116         * as device memory.  No other unexpected data must creep in.
117         * Ensure the rest of the current memory page is unused.
118         */
119        . = NEXT(4096);
120        __COHERENT_RAM_END__ = .;
121    } >RAM
122#endif
123
124    /*
125     * Define a linker symbol to mark end of the RW memory area for this
126     * image.
127     */
128    __RW_END__ = .;
129    __BL2U_END__ = .;
130
131    __BSS_SIZE__ = SIZEOF(.bss);
132
133    ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.")
134}
135