1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_config.h> 8 #include <plat_arm.h> 9 #include <smmu_v3.h> 10 #include "fvp_private.h" 11 12 #if LOAD_IMAGE_V2 bl31_early_platform_setup(void * from_bl2,void * plat_params_from_bl2)13void bl31_early_platform_setup(void *from_bl2, 14 void *plat_params_from_bl2) 15 #else 16 void bl31_early_platform_setup(bl31_params_t *from_bl2, 17 void *plat_params_from_bl2) 18 #endif 19 { 20 arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2); 21 22 /* Initialize the platform config for future decision making */ 23 fvp_config_setup(); 24 25 /* 26 * Initialize the correct interconnect for this cluster during cold 27 * boot. No need for locks as no other CPU is active. 28 */ 29 fvp_interconnect_init(); 30 31 /* 32 * Enable coherency in interconnect for the primary CPU's cluster. 33 * Earlier bootloader stages might already do this (e.g. Trusted 34 * Firmware's BL1 does it) but we can't assume so. There is no harm in 35 * executing this code twice anyway. 36 * FVP PSCI code will enable coherency for other clusters. 37 */ 38 fvp_interconnect_enable(); 39 40 /* On FVP RevC, intialize SMMUv3 */ 41 if (arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) 42 smmuv3_init(PLAT_FVP_SMMUV3_BASE); 43 } 44