1 /*
2  * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <arm_def.h>
8 #include <bl_common.h>
9 #include <console.h>
10 #include <plat_arm.h>
11 #include <platform_def.h>
12 #include <platform_tsp.h>
13 
14 #define BL32_END (unsigned long)(&__BL32_END__)
15 
16 /* Weak definitions may be overridden in specific ARM standard platform */
17 #pragma weak tsp_early_platform_setup
18 #pragma weak tsp_platform_setup
19 #pragma weak tsp_plat_arch_setup
20 
21 
22 /*******************************************************************************
23  * Initialize the UART
24  ******************************************************************************/
arm_tsp_early_platform_setup(void)25 void arm_tsp_early_platform_setup(void)
26 {
27 	/*
28 	 * Initialize a different console than already in use to display
29 	 * messages from TSP
30 	 */
31 	console_init(PLAT_ARM_TSP_UART_BASE, PLAT_ARM_TSP_UART_CLK_IN_HZ,
32 			ARM_CONSOLE_BAUDRATE);
33 }
34 
tsp_early_platform_setup(void)35 void tsp_early_platform_setup(void)
36 {
37 	arm_tsp_early_platform_setup();
38 }
39 
40 /*******************************************************************************
41  * Perform platform specific setup placeholder
42  ******************************************************************************/
tsp_platform_setup(void)43 void tsp_platform_setup(void)
44 {
45 	plat_arm_gic_driver_init();
46 }
47 
48 /*******************************************************************************
49  * Perform the very early platform specific architectural setup here. At the
50  * moment this is only intializes the MMU
51  ******************************************************************************/
tsp_plat_arch_setup(void)52 void tsp_plat_arch_setup(void)
53 {
54 	arm_setup_page_tables(BL32_BASE,
55 			      (BL32_END - BL32_BASE),
56 			      BL_CODE_BASE,
57 			      BL_CODE_END,
58 			      BL_RO_DATA_BASE,
59 			      BL_RO_DATA_END
60 #if USE_COHERENT_MEM
61 			      , BL_COHERENT_RAM_BASE,
62 			      BL_COHERENT_RAM_END
63 #endif
64 			      );
65 	enable_mmu_el1(0);
66 }
67