1 /*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <assert.h>
9 #include <bl_common.h>
10 #include <console.h>
11 #include <debug.h>
12 #include <dw_mmc.h>
13 #include <emmc.h>
14 #include <errno.h>
15 #include <gpio.h>
16 #include <hi6220.h>
17 #include <hi6553.h>
18 #include <mmio.h>
19 #include <pl061_gpio.h>
20 #include <platform.h>
21 #include <platform_def.h>
22 #include <sp804_delay_timer.h>
23 #include <string.h>
24 #include <tbbr/tbbr_img_desc.h>
25
26 #include "../../bl1/bl1_private.h"
27 #include "hikey_def.h"
28 #include "hikey_private.h"
29
30 /*
31 * Declarations of linker defined symbols which will help us find the layout
32 * of trusted RAM
33 */
34 extern unsigned long __COHERENT_RAM_START__;
35 extern unsigned long __COHERENT_RAM_END__;
36
37 /*
38 * The next 2 constants identify the extents of the coherent memory region.
39 * These addresses are used by the MMU setup code and therefore they must be
40 * page-aligned. It is the responsibility of the linker script to ensure that
41 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
42 * page-aligned addresses.
43 */
44 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
45 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
46
47 /* Data structure which holds the extents of the trusted RAM for BL1 */
48 static meminfo_t bl1_tzram_layout;
49
50 enum {
51 BOOT_NORMAL = 0,
52 BOOT_USB_DOWNLOAD,
53 BOOT_UART_DOWNLOAD,
54 };
55
bl1_plat_sec_mem_layout(void)56 meminfo_t *bl1_plat_sec_mem_layout(void)
57 {
58 return &bl1_tzram_layout;
59 }
60
61 #if LOAD_IMAGE_V2
62 /*******************************************************************************
63 * Function that takes a memory layout into which BL2 has been loaded and
64 * populates a new memory layout for BL2 that ensures that BL1's data sections
65 * resident in secure RAM are not visible to BL2.
66 ******************************************************************************/
bl1_init_bl2_mem_layout(const meminfo_t * bl1_mem_layout,meminfo_t * bl2_mem_layout)67 void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
68 meminfo_t *bl2_mem_layout)
69 {
70
71 assert(bl1_mem_layout != NULL);
72 assert(bl2_mem_layout != NULL);
73
74 /*
75 * Cannot remove BL1 RW data from the scope of memory visible to BL2
76 * like arm platforms because they overlap in hikey
77 */
78 bl2_mem_layout->total_base = BL2_BASE;
79 bl2_mem_layout->total_size = BL32_SRAM_LIMIT - BL2_BASE;
80
81 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
82 }
83 #endif /* LOAD_IMAGE_V2 */
84
85 /*
86 * Perform any BL1 specific platform actions.
87 */
bl1_early_platform_setup(void)88 void bl1_early_platform_setup(void)
89 {
90 /* Initialize the console to provide early debug support */
91 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
92
93 /* Allow BL1 to see the whole Trusted RAM */
94 bl1_tzram_layout.total_base = BL1_RW_BASE;
95 bl1_tzram_layout.total_size = BL1_RW_SIZE;
96
97 #if !LOAD_IMAGE_V2
98 /* Calculate how much RAM BL1 is using and how much remains free */
99 bl1_tzram_layout.free_base = BL1_RW_BASE;
100 bl1_tzram_layout.free_size = BL1_RW_SIZE;
101 reserve_mem(&bl1_tzram_layout.free_base,
102 &bl1_tzram_layout.free_size,
103 BL1_RAM_BASE,
104 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
105 #endif
106
107 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
108 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
109 }
110
111 /*
112 * Perform the very early platform specific architecture setup here. At the
113 * moment this only does basic initialization. Later architectural setup
114 * (bl1_arch_setup()) does not do anything platform specific.
115 */
bl1_plat_arch_setup(void)116 void bl1_plat_arch_setup(void)
117 {
118 hikey_init_mmu_el3(bl1_tzram_layout.total_base,
119 bl1_tzram_layout.total_size,
120 BL1_RO_BASE,
121 BL1_RO_LIMIT,
122 BL1_COHERENT_RAM_BASE,
123 BL1_COHERENT_RAM_LIMIT);
124 }
125
hikey_sp804_init(void)126 static void hikey_sp804_init(void)
127 {
128 uint32_t data;
129
130 /* select the clock of dual timer0 */
131 data = mmio_read_32(AO_SC_TIMER_EN0);
132 while (data & 3) {
133 data &= ~3;
134 data |= 3 << 16;
135 mmio_write_32(AO_SC_TIMER_EN0, data);
136 data = mmio_read_32(AO_SC_TIMER_EN0);
137 }
138 /* enable the pclk of dual timer0 */
139 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4);
140 while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)) {
141 mmio_write_32(AO_SC_PERIPH_CLKEN4, PCLK_TIMER1 | PCLK_TIMER0);
142 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4);
143 }
144 /* reset dual timer0 */
145 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
146 mmio_write_32(AO_SC_PERIPH_RSTEN4, PCLK_TIMER1 | PCLK_TIMER0);
147 do {
148 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
149 } while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0));
150 /* unreset dual timer0 */
151 mmio_write_32(AO_SC_PERIPH_RSTDIS4, PCLK_TIMER1 | PCLK_TIMER0);
152 do {
153 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
154 } while ((data & PCLK_TIMER1) || (data & PCLK_TIMER0));
155
156 sp804_timer_init(SP804_TIMER0_BASE, 10, 192);
157 }
158
hikey_gpio_init(void)159 static void hikey_gpio_init(void)
160 {
161 pl061_gpio_init();
162 pl061_gpio_register(GPIO0_BASE, 0);
163 pl061_gpio_register(GPIO1_BASE, 1);
164 pl061_gpio_register(GPIO2_BASE, 2);
165 pl061_gpio_register(GPIO3_BASE, 3);
166 pl061_gpio_register(GPIO4_BASE, 4);
167 pl061_gpio_register(GPIO5_BASE, 5);
168 pl061_gpio_register(GPIO6_BASE, 6);
169 pl061_gpio_register(GPIO7_BASE, 7);
170 pl061_gpio_register(GPIO8_BASE, 8);
171 pl061_gpio_register(GPIO9_BASE, 9);
172 pl061_gpio_register(GPIO10_BASE, 10);
173 pl061_gpio_register(GPIO11_BASE, 11);
174 pl061_gpio_register(GPIO12_BASE, 12);
175 pl061_gpio_register(GPIO13_BASE, 13);
176 pl061_gpio_register(GPIO14_BASE, 14);
177 pl061_gpio_register(GPIO15_BASE, 15);
178 pl061_gpio_register(GPIO16_BASE, 16);
179 pl061_gpio_register(GPIO17_BASE, 17);
180 pl061_gpio_register(GPIO18_BASE, 18);
181 pl061_gpio_register(GPIO19_BASE, 19);
182
183 /* Power on indicator LED (USER_LED1). */
184 gpio_set_direction(32, GPIO_DIR_OUT); /* LED1 */
185 gpio_set_value(32, GPIO_LEVEL_HIGH);
186 gpio_set_direction(33, GPIO_DIR_OUT); /* LED2 */
187 gpio_set_value(33, GPIO_LEVEL_LOW);
188 gpio_set_direction(34, GPIO_DIR_OUT); /* LED3 */
189 gpio_set_direction(35, GPIO_DIR_OUT); /* LED4 */
190 }
191
hikey_pmussi_init(void)192 static void hikey_pmussi_init(void)
193 {
194 uint32_t data;
195
196 /* Initialize PWR_HOLD GPIO */
197 gpio_set_direction(0, GPIO_DIR_OUT);
198 gpio_set_value(0, GPIO_LEVEL_LOW);
199
200 /*
201 * After reset, PMUSSI stays in reset mode.
202 * Now make it out of reset.
203 */
204 mmio_write_32(AO_SC_PERIPH_RSTDIS4,
205 AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N);
206 do {
207 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
208 } while (data & AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N);
209
210 /* Set PMUSSI clock latency for read operation. */
211 data = mmio_read_32(AO_SC_MCU_SUBSYS_CTRL3);
212 data &= ~AO_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
213 data |= AO_SC_MCU_SUBSYS_CTRL3_RCLK_3;
214 mmio_write_32(AO_SC_MCU_SUBSYS_CTRL3, data);
215
216 /* enable PMUSSI clock */
217 data = AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU |
218 AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_MCU;
219 mmio_write_32(AO_SC_PERIPH_CLKEN5, data);
220 data = AO_SC_PERIPH_CLKEN4_PCLK_PMUSSI;
221 mmio_write_32(AO_SC_PERIPH_CLKEN4, data);
222
223 gpio_set_value(0, GPIO_LEVEL_HIGH);
224 }
225
hikey_hi6553_init(void)226 static void hikey_hi6553_init(void)
227 {
228 uint8_t data;
229
230 mmio_write_8(HI6553_PERI_EN_MARK, 0x1e);
231 mmio_write_8(HI6553_NP_REG_ADJ1, 0);
232 data = DISABLE6_XO_CLK_CONN | DISABLE6_XO_CLK_NFC |
233 DISABLE6_XO_CLK_RF1 | DISABLE6_XO_CLK_RF2;
234 mmio_write_8(HI6553_DISABLE6_XO_CLK, data);
235
236 /* configure BUCK0 & BUCK1 */
237 mmio_write_8(HI6553_BUCK01_CTRL2, 0x5e);
238 mmio_write_8(HI6553_BUCK0_CTRL7, 0x10);
239 mmio_write_8(HI6553_BUCK1_CTRL7, 0x10);
240 mmio_write_8(HI6553_BUCK0_CTRL5, 0x1e);
241 mmio_write_8(HI6553_BUCK1_CTRL5, 0x1e);
242 mmio_write_8(HI6553_BUCK0_CTRL1, 0xfc);
243 mmio_write_8(HI6553_BUCK1_CTRL1, 0xfc);
244
245 /* configure BUCK2 */
246 mmio_write_8(HI6553_BUCK2_REG1, 0x4f);
247 mmio_write_8(HI6553_BUCK2_REG5, 0x99);
248 mmio_write_8(HI6553_BUCK2_REG6, 0x45);
249 mdelay(1);
250 mmio_write_8(HI6553_VSET_BUCK2_ADJ, 0x22);
251 mdelay(1);
252
253 /* configure BUCK3 */
254 mmio_write_8(HI6553_BUCK3_REG3, 0x02);
255 mmio_write_8(HI6553_BUCK3_REG5, 0x99);
256 mmio_write_8(HI6553_BUCK3_REG6, 0x41);
257 mmio_write_8(HI6553_VSET_BUCK3_ADJ, 0x02);
258 mdelay(1);
259
260 /* configure BUCK4 */
261 mmio_write_8(HI6553_BUCK4_REG2, 0x9a);
262 mmio_write_8(HI6553_BUCK4_REG5, 0x99);
263 mmio_write_8(HI6553_BUCK4_REG6, 0x45);
264
265 /* configure LDO20 */
266 mmio_write_8(HI6553_LDO20_REG_ADJ, 0x50);
267
268 mmio_write_8(HI6553_NP_REG_CHG, 0x0f);
269 mmio_write_8(HI6553_CLK_TOP0, 0x06);
270 mmio_write_8(HI6553_CLK_TOP3, 0xc0);
271 mmio_write_8(HI6553_CLK_TOP4, 0x00);
272
273 /* configure LDO7 & LDO10 for SD slot */
274 /* enable LDO7 */
275 data = mmio_read_8(HI6553_LDO7_REG_ADJ);
276 data = (data & 0xf8) | 0x2;
277 mmio_write_8(HI6553_LDO7_REG_ADJ, data);
278 mdelay(5);
279 mmio_write_8(HI6553_ENABLE2_LDO1_8, 1 << 6);
280 mdelay(5);
281 /* enable LDO10 */
282 data = mmio_read_8(HI6553_LDO10_REG_ADJ);
283 data = (data & 0xf8) | 0x5;
284 mmio_write_8(HI6553_LDO10_REG_ADJ, data);
285 mdelay(5);
286 mmio_write_8(HI6553_ENABLE3_LDO9_16, 1 << 1);
287 mdelay(5);
288 /* enable LDO15 */
289 data = mmio_read_8(HI6553_LDO15_REG_ADJ);
290 data = (data & 0xf8) | 0x4;
291 mmio_write_8(HI6553_LDO15_REG_ADJ, data);
292 mmio_write_8(HI6553_ENABLE3_LDO9_16, 1 << 6);
293 mdelay(5);
294 /* enable LDO19 */
295 data = mmio_read_8(HI6553_LDO19_REG_ADJ);
296 data |= 0x7;
297 mmio_write_8(HI6553_LDO19_REG_ADJ, data);
298 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 2);
299 mdelay(5);
300 /* enable LDO21 */
301 data = mmio_read_8(HI6553_LDO21_REG_ADJ);
302 data = (data & 0xf8) | 0x3;
303 mmio_write_8(HI6553_LDO21_REG_ADJ, data);
304 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 4);
305 mdelay(5);
306 /* enable LDO22 */
307 data = mmio_read_8(HI6553_LDO22_REG_ADJ);
308 data = (data & 0xf8) | 0x7;
309 mmio_write_8(HI6553_LDO22_REG_ADJ, data);
310 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 5);
311 mdelay(5);
312
313 /* select 32.764KHz */
314 mmio_write_8(HI6553_CLK19M2_600_586_EN, 0x01);
315
316 /* Disable vbus_det interrupts */
317 data = mmio_read_8(HI6553_IRQ2_MASK);
318 data = data | 0x3;
319 mmio_write_8(HI6553_IRQ2_MASK, data);
320 }
321
init_mmc0_pll(void)322 static void init_mmc0_pll(void)
323 {
324 unsigned int data;
325
326 /* select SYSPLL as the source of MMC0 */
327 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
328 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 5 | 1 << 21);
329 do {
330 data = mmio_read_32(PERI_SC_CLK_SEL0);
331 } while (!(data & (1 << 5)));
332 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
333 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 29);
334 do {
335 data = mmio_read_32(PERI_SC_CLK_SEL0);
336 } while (data & (1 << 13));
337
338 mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 0));
339 do {
340 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
341 } while (!(data & (1 << 0)));
342
343 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
344 data |= 1 << 1;
345 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
346
347 do {
348 mmio_write_32(PERI_SC_CLKCFG8BIT1, (1 << 7) | 0xb);
349 data = mmio_read_32(PERI_SC_CLKCFG8BIT1);
350 } while ((data & 0xb) != 0xb);
351 }
352
reset_mmc0_clk(void)353 static void reset_mmc0_clk(void)
354 {
355 unsigned int data;
356
357 /* disable mmc0 bus clock */
358 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0);
359 do {
360 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
361 } while (data & PERI_CLK0_MMC0);
362 /* enable mmc0 bus clock */
363 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0);
364 do {
365 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
366 } while (!(data & PERI_CLK0_MMC0));
367 /* reset mmc0 clock domain */
368 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0);
369
370 /* bypass mmc0 clock phase */
371 data = mmio_read_32(PERI_SC_PERIPH_CTRL2);
372 data |= 3;
373 mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
374
375 /* disable low power */
376 data = mmio_read_32(PERI_SC_PERIPH_CTRL13);
377 data |= 1 << 3;
378 mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
379 do {
380 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
381 } while (!(data & PERI_RST0_MMC0));
382
383 /* unreset mmc0 clock domain */
384 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0);
385 do {
386 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
387 } while (data & PERI_RST0_MMC0);
388 }
389
init_media_clk(void)390 static void init_media_clk(void)
391 {
392 unsigned int data, value;
393
394 data = mmio_read_32(PMCTRL_MEDPLLCTRL);
395 data |= 1;
396 mmio_write_32(PMCTRL_MEDPLLCTRL, data);
397
398 for (;;) {
399 data = mmio_read_32(PMCTRL_MEDPLLCTRL);
400 value = 1 << 28;
401 if ((data & value) == value)
402 break;
403 }
404
405 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
406 data = 1 << 10;
407 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
408 }
409
init_mmc1_pll(void)410 static void init_mmc1_pll(void)
411 {
412 uint32_t data;
413
414 /* select SYSPLL as the source of MMC1 */
415 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
416 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 11 | 1 << 27);
417 do {
418 data = mmio_read_32(PERI_SC_CLK_SEL0);
419 } while (!(data & (1 << 11)));
420 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
421 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 30);
422 do {
423 data = mmio_read_32(PERI_SC_CLK_SEL0);
424 } while (data & (1 << 14));
425
426 mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 1));
427 do {
428 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
429 } while (!(data & (1 << 1)));
430
431 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
432 data |= 1 << 2;
433 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
434
435 do {
436 /* 1.2GHz / 50 = 24MHz */
437 mmio_write_32(PERI_SC_CLKCFG8BIT2, 0x31 | (1 << 7));
438 data = mmio_read_32(PERI_SC_CLKCFG8BIT2);
439 } while ((data & 0x31) != 0x31);
440 }
441
reset_mmc1_clk(void)442 static void reset_mmc1_clk(void)
443 {
444 unsigned int data;
445
446 /* disable mmc1 bus clock */
447 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC1);
448 do {
449 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
450 } while (data & PERI_CLK0_MMC1);
451 /* enable mmc1 bus clock */
452 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC1);
453 do {
454 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
455 } while (!(data & PERI_CLK0_MMC1));
456 /* reset mmc1 clock domain */
457 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC1);
458
459 /* bypass mmc1 clock phase */
460 data = mmio_read_32(PERI_SC_PERIPH_CTRL2);
461 data |= 3 << 2;
462 mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
463
464 /* disable low power */
465 data = mmio_read_32(PERI_SC_PERIPH_CTRL13);
466 data |= 1 << 4;
467 mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
468 do {
469 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
470 } while (!(data & PERI_RST0_MMC1));
471
472 /* unreset mmc0 clock domain */
473 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC1);
474 do {
475 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
476 } while (data & PERI_RST0_MMC1);
477 }
478
479 /* Initialize PLL of both eMMC and SD controllers. */
hikey_mmc_pll_init(void)480 static void hikey_mmc_pll_init(void)
481 {
482 init_mmc0_pll();
483 reset_mmc0_clk();
484 init_media_clk();
485
486 dsb();
487
488 init_mmc1_pll();
489 reset_mmc1_clk();
490 }
491
hikey_rtc_init(void)492 static void hikey_rtc_init(void)
493 {
494 uint32_t data;
495
496 data = mmio_read_32(AO_SC_PERIPH_CLKEN4);
497 data |= AO_SC_PERIPH_RSTDIS4_RESET_RTC0_N;
498 mmio_write_32(AO_SC_PERIPH_CLKEN4, data);
499 }
500
501 /*
502 * Function which will perform any remaining platform-specific setup that can
503 * occur after the MMU and data cache have been enabled.
504 */
bl1_platform_setup(void)505 void bl1_platform_setup(void)
506 {
507 dw_mmc_params_t params;
508
509 assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) &&
510 ((SRAM_BASE + SRAM_SIZE) >=
511 (HIKEY_BL1_MMC_DATA_BASE + HIKEY_BL1_MMC_DATA_SIZE)));
512 hikey_sp804_init();
513 hikey_gpio_init();
514 hikey_pmussi_init();
515 hikey_hi6553_init();
516
517 hikey_rtc_init();
518
519 hikey_mmc_pll_init();
520
521 memset(¶ms, 0, sizeof(dw_mmc_params_t));
522 params.reg_base = DWMMC0_BASE;
523 params.desc_base = HIKEY_BL1_MMC_DESC_BASE;
524 params.desc_size = 1 << 20;
525 params.clk_rate = 24 * 1000 * 1000;
526 params.bus_width = EMMC_BUS_WIDTH_8;
527 params.flags = EMMC_FLAG_CMD23;
528 dw_mmc_init(¶ms);
529
530 hikey_io_setup();
531 }
532
533 /*
534 * The following function checks if Firmware update is needed,
535 * by checking if TOC in FIP image is valid or not.
536 */
bl1_plat_get_next_image_id(void)537 unsigned int bl1_plat_get_next_image_id(void)
538 {
539 int32_t boot_mode;
540 unsigned int ret;
541
542 boot_mode = mmio_read_32(ONCHIPROM_PARAM_BASE);
543 switch (boot_mode) {
544 case BOOT_NORMAL:
545 ret = BL2_IMAGE_ID;
546 break;
547 case BOOT_USB_DOWNLOAD:
548 case BOOT_UART_DOWNLOAD:
549 ret = NS_BL1U_IMAGE_ID;
550 break;
551 default:
552 WARN("Invalid boot mode is found:%d\n", boot_mode);
553 panic();
554 }
555 return ret;
556 }
557
bl1_plat_get_image_desc(unsigned int image_id)558 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id)
559 {
560 unsigned int index = 0;
561
562 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) {
563 if (bl1_tbbr_image_descs[index].image_id == image_id)
564 return &bl1_tbbr_image_descs[index];
565
566 index++;
567 }
568
569 return NULL;
570 }
571
bl1_plat_set_ep_info(unsigned int image_id,entry_point_info_t * ep_info)572 void bl1_plat_set_ep_info(unsigned int image_id,
573 entry_point_info_t *ep_info)
574 {
575 unsigned int data = 0;
576
577 if (image_id == BL2_IMAGE_ID)
578 return;
579 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE);
580 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data));
581 do {
582 data |= 3 << 20;
583 __asm__ volatile ("msr cpacr_el1, %0" : : "r"(data));
584 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data));
585 } while ((data & (3 << 20)) != (3 << 20));
586 INFO("cpacr_el1:0x%x\n", data);
587
588 ep_info->args.arg0 = 0xffff & read_mpidr();
589 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
590 DISABLE_ALL_EXCEPTIONS);
591 }
592