1 /*
2  * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef __TEGRA_DEF_H__
8 #define __TEGRA_DEF_H__
9 
10 #include <utils_def.h>
11 
12 /*******************************************************************************
13  * MCE apertures used by the ARI interface
14  *
15  * Aperture 0 - Cpu0 (ARM Cortex A-57)
16  * Aperture 1 - Cpu1 (ARM Cortex A-57)
17  * Aperture 2 - Cpu2 (ARM Cortex A-57)
18  * Aperture 3 - Cpu3 (ARM Cortex A-57)
19  * Aperture 4 - Cpu4 (Denver15)
20  * Aperture 5 - Cpu5 (Denver15)
21  ******************************************************************************/
22 #define MCE_ARI_APERTURE_0_OFFSET	U(0x0)
23 #define MCE_ARI_APERTURE_1_OFFSET	U(0x10000)
24 #define MCE_ARI_APERTURE_2_OFFSET	U(0x20000)
25 #define MCE_ARI_APERTURE_3_OFFSET	U(0x30000)
26 #define MCE_ARI_APERTURE_4_OFFSET	U(0x40000)
27 #define MCE_ARI_APERTURE_5_OFFSET	U(0x50000)
28 #define MCE_ARI_APERTURE_OFFSET_MAX	MCE_APERTURE_5_OFFSET
29 
30 /* number of apertures */
31 #define MCE_ARI_APERTURES_MAX		U(6)
32 
33 /* each ARI aperture is 64KB */
34 #define MCE_ARI_APERTURE_SIZE		U(0x10000)
35 
36 /*******************************************************************************
37  * CPU core id macros for the MCE_ONLINE_CORE ARI
38  ******************************************************************************/
39 #define MCE_CORE_ID_MAX			U(8)
40 #define MCE_CORE_ID_MASK		U(0x7)
41 
42 /*******************************************************************************
43  * These values are used by the PSCI implementation during the `CPU_SUSPEND`
44  * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
45  * parameter.
46  ******************************************************************************/
47 #define PSTATE_ID_CORE_IDLE		U(6)
48 #define PSTATE_ID_CORE_POWERDN		U(7)
49 #define PSTATE_ID_SOC_POWERDN		U(2)
50 
51 /*******************************************************************************
52  * Platform power states (used by PSCI framework)
53  *
54  * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
55  * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
56  ******************************************************************************/
57 #define PLAT_MAX_RET_STATE		U(1)
58 #define PLAT_MAX_OFF_STATE		U(8)
59 
60 /*******************************************************************************
61  * Secure IRQ definitions
62  ******************************************************************************/
63 #define TEGRA186_TOP_WDT_IRQ		U(49)
64 #define TEGRA186_AON_WDT_IRQ		U(50)
65 
66 #define TEGRA186_SEC_IRQ_TARGET_MASK	U(0xF3) /* 4 A57 - 2 Denver */
67 
68 /*******************************************************************************
69  * Tegra Miscellanous register constants
70  ******************************************************************************/
71 #define TEGRA_MISC_BASE			U(0x00100000)
72 #define  HARDWARE_REVISION_OFFSET	U(0x4)
73 
74 #define  MISCREG_PFCFG			U(0x200C)
75 
76 /*******************************************************************************
77  * Tegra TSA Controller constants
78  ******************************************************************************/
79 #define TEGRA_TSA_BASE			U(0x02400000)
80 
81 /*******************************************************************************
82  * TSA configuration registers
83  ******************************************************************************/
84 #define TSA_CONFIG_STATIC0_CSW_SESWR			U(0x4010)
85 #define  TSA_CONFIG_STATIC0_CSW_SESWR_RESET		U(0x1100)
86 #define TSA_CONFIG_STATIC0_CSW_ETRW			U(0x4038)
87 #define  TSA_CONFIG_STATIC0_CSW_ETRW_RESET		U(0x1100)
88 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB			U(0x5010)
89 #define  TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET		U(0x1100)
90 #define TSA_CONFIG_STATIC0_CSW_AXISW			U(0x7008)
91 #define  TSA_CONFIG_STATIC0_CSW_AXISW_RESET		U(0x1100)
92 #define TSA_CONFIG_STATIC0_CSW_HDAW			U(0xA008)
93 #define  TSA_CONFIG_STATIC0_CSW_HDAW_RESET		U(0x100)
94 #define TSA_CONFIG_STATIC0_CSW_AONDMAW			U(0xB018)
95 #define  TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET		U(0x1100)
96 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW			U(0xD018)
97 #define  TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET		U(0x1100)
98 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW			U(0xD028)
99 #define  TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET		U(0x1100)
100 #define TSA_CONFIG_STATIC0_CSW_APEDMAW			U(0x12018)
101 #define  TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET		U(0x1100)
102 #define TSA_CONFIG_STATIC0_CSW_UFSHCW			U(0x13008)
103 #define  TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET		U(0x1100)
104 #define TSA_CONFIG_STATIC0_CSW_AFIW			U(0x13018)
105 #define  TSA_CONFIG_STATIC0_CSW_AFIW_RESET		U(0x1100)
106 #define TSA_CONFIG_STATIC0_CSW_SATAW			U(0x13028)
107 #define  TSA_CONFIG_STATIC0_CSW_SATAW_RESET		U(0x1100)
108 #define TSA_CONFIG_STATIC0_CSW_EQOSW			U(0x13038)
109 #define  TSA_CONFIG_STATIC0_CSW_EQOSW_RESET		U(0x1100)
110 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW		U(0x15008)
111 #define  TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET		U(0x1100)
112 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW		U(0x15018)
113 #define  TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET	U(0x1100)
114 
115 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK		(U(0x3) << 11)
116 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU		(U(0) << 11)
117 
118 /*******************************************************************************
119  * Tegra Memory Controller constants
120  ******************************************************************************/
121 #define TEGRA_MC_STREAMID_BASE		U(0x02C00000)
122 #define TEGRA_MC_BASE			U(0x02C10000)
123 
124 /* General Security Carveout register macros */
125 #define MC_GSC_CONFIG_REGS_SIZE		U(0x40)
126 #define MC_GSC_LOCK_CFG_SETTINGS_BIT	(U(1) << 1)
127 #define MC_GSC_ENABLE_TZ_LOCK_BIT	(U(1) << 0)
128 #define MC_GSC_SIZE_RANGE_4KB_SHIFT	U(27)
129 #define MC_GSC_BASE_LO_SHIFT		U(12)
130 #define MC_GSC_BASE_LO_MASK		U(0xFFFFF)
131 #define MC_GSC_BASE_HI_SHIFT		U(0)
132 #define MC_GSC_BASE_HI_MASK		U(3)
133 
134 /* TZDRAM carveout configuration registers */
135 #define MC_SECURITY_CFG0_0		U(0x70)
136 #define MC_SECURITY_CFG1_0		U(0x74)
137 #define MC_SECURITY_CFG3_0		U(0x9BC)
138 
139 /* Video Memory carveout configuration registers */
140 #define MC_VIDEO_PROTECT_BASE_HI	U(0x978)
141 #define MC_VIDEO_PROTECT_BASE_LO	U(0x648)
142 #define MC_VIDEO_PROTECT_SIZE_MB	U(0x64C)
143 
144 /*
145  * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
146  * non-overlapping Video memory region
147  */
148 #define MC_VIDEO_PROTECT_CLEAR_CFG	U(0x25A0)
149 #define MC_VIDEO_PROTECT_CLEAR_BASE_LO	U(0x25A4)
150 #define MC_VIDEO_PROTECT_CLEAR_BASE_HI	U(0x25A8)
151 #define MC_VIDEO_PROTECT_CLEAR_SIZE	U(0x25AC)
152 #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0	U(0x25B0)
153 
154 /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
155 #define MC_TZRAM_CARVEOUT_CFG		U(0x2190)
156 #define MC_TZRAM_BASE_LO		U(0x2194)
157 #define MC_TZRAM_BASE_HI		U(0x2198)
158 #define MC_TZRAM_SIZE			U(0x219C)
159 #define MC_TZRAM_CLIENT_ACCESS_CFG0	U(0x21A0)
160 
161 /*******************************************************************************
162  * Tegra UART Controller constants
163  ******************************************************************************/
164 #define TEGRA_UARTA_BASE		U(0x03100000)
165 #define TEGRA_UARTB_BASE		U(0x03110000)
166 #define TEGRA_UARTC_BASE		U(0x0C280000)
167 #define TEGRA_UARTD_BASE		U(0x03130000)
168 #define TEGRA_UARTE_BASE		U(0x03140000)
169 #define TEGRA_UARTF_BASE		U(0x03150000)
170 #define TEGRA_UARTG_BASE		U(0x0C290000)
171 
172 /*******************************************************************************
173  * Tegra Fuse Controller related constants
174  ******************************************************************************/
175 #define TEGRA_FUSE_BASE			U(0x03820000)
176 #define  OPT_SUBREVISION		U(0x248)
177 #define  SUBREVISION_MASK		U(0xFF)
178 
179 /*******************************************************************************
180  * GICv2 & interrupt handling related constants
181  ******************************************************************************/
182 #define TEGRA_GICD_BASE			U(0x03881000)
183 #define TEGRA_GICC_BASE			U(0x03882000)
184 
185 /*******************************************************************************
186  * Security Engine related constants
187  ******************************************************************************/
188 #define TEGRA_SE0_BASE			U(0x03AC0000)
189 #define  SE_MUTEX_WATCHDOG_NS_LIMIT	U(0x6C)
190 #define TEGRA_PKA1_BASE			U(0x03AD0000)
191 #define  PKA_MUTEX_WATCHDOG_NS_LIMIT	U(0x8144)
192 #define TEGRA_RNG1_BASE			U(0x03AE0000)
193 #define  RNG_MUTEX_WATCHDOG_NS_LIMIT	U(0xFE0)
194 
195 /*******************************************************************************
196  * Tegra Clock and Reset Controller constants
197  ******************************************************************************/
198 #define TEGRA_CAR_RESET_BASE		U(0x05000000)
199 #define TEGRA_GPU_RESET_REG_OFFSET	U(0x30)
200 #define  GPU_RESET_BIT			(U(1) << 0)
201 
202 /*******************************************************************************
203  * Tegra micro-seconds timer constants
204  ******************************************************************************/
205 #define TEGRA_TMRUS_BASE		U(0x0C2E0000)
206 #define TEGRA_TMRUS_SIZE		U(0x1000)
207 
208 /*******************************************************************************
209  * Tegra Power Mgmt Controller constants
210  ******************************************************************************/
211 #define TEGRA_PMC_BASE			U(0x0C360000)
212 
213 /*******************************************************************************
214  * Tegra scratch registers constants
215  ******************************************************************************/
216 #define TEGRA_SCRATCH_BASE		U(0x0C390000)
217 #define  SECURE_SCRATCH_RSV1_LO		U(0x658)
218 #define  SECURE_SCRATCH_RSV1_HI		U(0x65C)
219 #define  SECURE_SCRATCH_RSV6		U(0x680)
220 #define  SECURE_SCRATCH_RSV11_LO	U(0x6A8)
221 #define  SECURE_SCRATCH_RSV11_HI	U(0x6AC)
222 #define  SECURE_SCRATCH_RSV53_LO	U(0x7F8)
223 #define  SECURE_SCRATCH_RSV53_HI	U(0x7FC)
224 #define  SECURE_SCRATCH_RSV54_HI	U(0x804)
225 #define  SECURE_SCRATCH_RSV55_LO	U(0x808)
226 #define  SECURE_SCRATCH_RSV55_HI	U(0x80C)
227 
228 /*******************************************************************************
229  * Tegra Memory Mapped Control Register Access constants
230  ******************************************************************************/
231 #define TEGRA_MMCRAB_BASE		U(0x0E000000)
232 
233 /*******************************************************************************
234  * Tegra Memory Mapped Activity Monitor Register Access constants
235  ******************************************************************************/
236 #define TEGRA_ARM_ACTMON_CTR_BASE	U(0x0E060000)
237 #define TEGRA_DENVER_ACTMON_CTR_BASE	U(0x0E070000)
238 
239 /*******************************************************************************
240  * Tegra SMMU Controller constants
241  ******************************************************************************/
242 #define TEGRA_SMMU0_BASE		U(0x12000000)
243 
244 /*******************************************************************************
245  * Tegra TZRAM constants
246  ******************************************************************************/
247 #define TEGRA_TZRAM_BASE		U(0x30000000)
248 #define TEGRA_TZRAM_SIZE		U(0x40000)
249 
250 #endif /* __TEGRA_DEF_H__ */
251