1#/** @file 2# 3# Copyright (c) 2011-2016, ARM Limited. All rights reserved. 4# Copyright (c) 2015, Intel Corporation. All rights reserved. 5# 6# This program and the accompanying materials 7# are licensed and made available under the terms and conditions of the BSD License 8# which accompanies this distribution. The full text of the license may be found at 9# http://opensource.org/licenses/bsd-license.php 10# 11# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13# 14#**/ 15 16[Defines] 17 DEC_SPECIFICATION = 0x00010005 18 PACKAGE_NAME = ArmPlatformPkg 19 PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b 20 PACKAGE_VERSION = 0.1 21 22################################################################################ 23# 24# Include Section - list of Include Paths that are provided by this package. 25# Comments are used for Keywords and Module Types. 26# 27# Supported Module Types: 28# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION 29# 30################################################################################ 31[Includes.common] 32 Include # Root include for the package 33 34[Guids.common] 35 gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } } 36 # 37 # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf 38 # 39 gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } } 40 41 gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } } 42 43[PcdsFeatureFlag.common] 44 # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0. 45 gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012 46 47 gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001 48 gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002 49 gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004 50 51 gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C 52 53 # Disable the GOP controller on ExitBootServices(). By default the value is FALSE, 54 # we assume the OS will handle the FrameBuffer from the UEFI GOP information. 55 gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D 56 57 # Enable Legacy Linux support in the BDS 58 gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|FALSE|BOOLEAN|0x0000002E 59 60[PcdsFixedAtBuild.common] 61 gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039 62 gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038 63 64 # Stack for CPU Cores in Secure Mode 65 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT64|0x00000005 66 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036 67 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006 68 69 # Stack for CPU Cores in Non Secure Mode 70 gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009 71 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037 72 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A 73 74 # Size of the region used by UEFI in permanent memory (Reserved 128MB by default) 75 gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015 76 77 # Boot Monitor FileSystem 78 gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A 79 80 # 81 # ARM Primecells 82 # 83 84 ## SP804 DualTimer 85 gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D 86 gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E 87 gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A 88 gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B 89 gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C 90 91 ## SP805 Watchdog 92 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023 93 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021 94 95 ## PL011 UART 96 gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F 97 gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020 98 gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D 99 gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F 100 101 ## PL011 Serial Debug UART 102 gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030 103 gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|0x00000000|UINT64|0x00000031 104 gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|0x00000000|UINT32|0x00000032 105 106 ## PL061 GPIO 107 gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025 108 109 ## PL111 Lcd & HdLcd 110 gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026 111 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027 112 113 ## PL180 MCI 114 gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028 115 gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029 116 117 # 118 # BDS - Boot Manager 119 # 120 gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019 121 gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C 122 gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D 123 gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F 124 125 gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B 126 gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C 127 128[PcdsFixedAtBuild.common,PcdsDynamic.common] 129 ## PL031 RealTimeClock 130 gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024 131 gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022 132 133[PcdsFixedAtBuild.ARM] 134 # Stack for CPU Cores in Secure Monitor Mode 135 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007 136 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008 137 138[PcdsFixedAtBuild.AARCH64] 139 # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64. 140 # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize 141 # and PcdCPUCoreSecSecondaryStackSize 142 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007 143 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008 144 145