1 /*++ 2 3 Copyright (c) 2004 - 2007, Intel Corporation. All rights reserved.<BR> 4 This program and the accompanying materials 5 are licensed and made available under the terms and conditions of the BSD License 6 which accompanies this distribution. The full text of the license may be found at 7 http://opensource.org/licenses/bsd-license.php 8 9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 12 Module Name: 13 14 pci22.h 15 16 Abstract: 17 Support for PCI 2.2 standard. 18 19 Revision History 20 21 --*/ 22 23 #ifndef _PCI22_H 24 #define _PCI22_H 25 26 #define PCI_MAX_SEGMENT 0 27 28 #define PCI_MAX_BUS 255 29 30 #define PCI_MAX_DEVICE 31 31 #define PCI_MAX_FUNC 7 32 33 // 34 // Command 35 // 36 #define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20 37 38 #pragma pack(1) 39 typedef struct { 40 UINT16 VendorId; 41 UINT16 DeviceId; 42 UINT16 Command; 43 UINT16 Status; 44 UINT8 RevisionID; 45 UINT8 ClassCode[3]; 46 UINT8 CacheLineSize; 47 UINT8 LatencyTimer; 48 UINT8 HeaderType; 49 UINT8 BIST; 50 } PCI_DEVICE_INDEPENDENT_REGION; 51 52 typedef struct { 53 UINT32 Bar[6]; 54 UINT32 CISPtr; 55 UINT16 SubsystemVendorID; 56 UINT16 SubsystemID; 57 UINT32 ExpansionRomBar; 58 UINT8 CapabilityPtr; 59 UINT8 Reserved1[3]; 60 UINT32 Reserved2; 61 UINT8 InterruptLine; 62 UINT8 InterruptPin; 63 UINT8 MinGnt; 64 UINT8 MaxLat; 65 } PCI_DEVICE_HEADER_TYPE_REGION; 66 67 typedef struct { 68 PCI_DEVICE_INDEPENDENT_REGION Hdr; 69 PCI_DEVICE_HEADER_TYPE_REGION Device; 70 } PCI_TYPE00; 71 72 typedef struct { 73 UINT32 Bar[2]; 74 UINT8 PrimaryBus; 75 UINT8 SecondaryBus; 76 UINT8 SubordinateBus; 77 UINT8 SecondaryLatencyTimer; 78 UINT8 IoBase; 79 UINT8 IoLimit; 80 UINT16 SecondaryStatus; 81 UINT16 MemoryBase; 82 UINT16 MemoryLimit; 83 UINT16 PrefetchableMemoryBase; 84 UINT16 PrefetchableMemoryLimit; 85 UINT32 PrefetchableBaseUpper32; 86 UINT32 PrefetchableLimitUpper32; 87 UINT16 IoBaseUpper16; 88 UINT16 IoLimitUpper16; 89 UINT8 CapabilityPtr; 90 UINT8 Reserved[3]; 91 UINT32 ExpansionRomBAR; 92 UINT8 InterruptLine; 93 UINT8 InterruptPin; 94 UINT16 BridgeControl; 95 } PCI_BRIDGE_CONTROL_REGISTER; 96 97 typedef struct { 98 PCI_DEVICE_INDEPENDENT_REGION Hdr; 99 PCI_BRIDGE_CONTROL_REGISTER Bridge; 100 } PCI_TYPE01; 101 102 typedef union { 103 PCI_TYPE00 Device; 104 PCI_TYPE01 Bridge; 105 } PCI_TYPE_GENERIC; 106 107 typedef struct { 108 UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base 109 // Address Register 110 // 111 UINT16 Reserved; 112 UINT16 SecondaryStatus; // Secondary Status 113 UINT8 PciBusNumber; // PCI Bus Number 114 UINT8 CardBusBusNumber; // CardBus Bus Number 115 UINT8 SubordinateBusNumber; // Subordinate Bus Number 116 UINT8 CardBusLatencyTimer; // CardBus Latency Timer 117 UINT32 MemoryBase0; // Memory Base Register 0 118 UINT32 MemoryLimit0; // Memory Limit Register 0 119 UINT32 MemoryBase1; 120 UINT32 MemoryLimit1; 121 UINT32 IoBase0; 122 UINT32 IoLimit0; // I/O Base Register 0 123 UINT32 IoBase1; // I/O Limit Register 0 124 UINT32 IoLimit1; 125 UINT8 InterruptLine; // Interrupt Line 126 UINT8 InterruptPin; // Interrupt Pin 127 UINT16 BridgeControl; // Bridge Control 128 } PCI_CARDBUS_CONTROL_REGISTER; 129 130 // 131 // Definitions of PCI class bytes and manipulation macros. 132 // 133 #define PCI_CLASS_OLD 0x00 134 #define PCI_CLASS_OLD_OTHER 0x00 135 #define PCI_CLASS_OLD_VGA 0x01 136 137 #define PCI_CLASS_MASS_STORAGE 0x01 138 #define PCI_CLASS_MASS_STORAGE_SCSI 0x00 139 #define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete 140 #define PCI_CLASS_IDE 0x01 141 #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02 142 #define PCI_CLASS_MASS_STORAGE_IPI 0x03 143 #define PCI_CLASS_MASS_STORAGE_RAID 0x04 144 #define PCI_CLASS_MASS_STORAGE_OTHER 0x80 145 146 #define PCI_CLASS_NETWORK 0x02 147 #define PCI_CLASS_NETWORK_ETHERNET 0x00 148 #define PCI_CLASS_ETHERNET 0x00 // obsolete 149 #define PCI_CLASS_NETWORK_TOKENRING 0x01 150 #define PCI_CLASS_NETWORK_FDDI 0x02 151 #define PCI_CLASS_NETWORK_ATM 0x03 152 #define PCI_CLASS_NETWORK_ISDN 0x04 153 #define PCI_CLASS_NETWORK_OTHER 0x80 154 155 #define PCI_CLASS_DISPLAY 0x03 156 #define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete 157 #define PCI_CLASS_DISPLAY_VGA 0x00 158 #define PCI_CLASS_VGA 0x00 // obsolete 159 #define PCI_CLASS_DISPLAY_XGA 0x01 160 #define PCI_CLASS_DISPLAY_3D 0x02 161 #define PCI_CLASS_DISPLAY_OTHER 0x80 162 #define PCI_CLASS_DISPLAY_GFX 0x80 163 #define PCI_CLASS_GFX 0x80 // obsolete 164 165 #define PCI_CLASS_BRIDGE 0x06 166 #define PCI_CLASS_BRIDGE_HOST 0x00 167 #define PCI_CLASS_BRIDGE_ISA 0x01 168 #define PCI_CLASS_ISA 0x01 // obsolete 169 #define PCI_CLASS_BRIDGE_EISA 0x02 170 #define PCI_CLASS_BRIDGE_MCA 0x03 171 #define PCI_CLASS_BRIDGE_P2P 0x04 172 #define PCI_CLASS_BRIDGE_PCMCIA 0x05 173 #define PCI_CLASS_BRIDGE_NUBUS 0x06 174 #define PCI_CLASS_BRIDGE_CARDBUS 0x07 175 #define PCI_CLASS_BRIDGE_RACEWAY 0x08 176 #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80 177 #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete 178 179 #define PCI_CLASS_SCC 0x07 // Simple communications controllers 180 #define PCI_SUBCLASS_SERIAL 0x00 181 #define PCI_IF_GENERIC_XT 0x00 182 #define PCI_IF_16450 0x01 183 #define PCI_IF_16550 0x02 184 #define PCI_IF_16650 0x03 185 #define PCI_IF_16750 0x04 186 #define PCI_IF_16850 0x05 187 #define PCI_IF_16950 0x06 188 #define PCI_SUBCLASS_PARALLEL 0x01 189 #define PCI_IF_PARALLEL_PORT 0x00 190 #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01 191 #define PCI_IF_ECP_PARALLEL_PORT 0x02 192 #define PCI_IF_1284_CONTROLLER 0x03 193 #define PCI_IF_1284_DEVICE 0xFE 194 #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02 195 #define PCI_SUBCLASS_MODEM 0x03 196 #define PCI_IF_GENERIC_MODEM 0x00 197 #define PCI_IF_16450_MODEM 0x01 198 #define PCI_IF_16550_MODEM 0x02 199 #define PCI_IF_16650_MODEM 0x03 200 #define PCI_IF_16750_MODEM 0x04 201 #define PCI_SUBCLASS_OTHER 0x80 202 203 #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08 204 #define PCI_SUBCLASS_PIC 0x00 205 #define PCI_IF_8259_PIC 0x00 206 #define PCI_IF_ISA_PIC 0x01 207 #define PCI_IF_EISA_PIC 0x02 208 #define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory. 209 #define PCI_IF_APIC_CONTROLLER2 0x20 210 #define PCI_SUBCLASS_TIMER 0x02 211 #define PCI_IF_8254_TIMER 0x00 212 #define PCI_IF_ISA_TIMER 0x01 213 #define PCI_EISA_TIMER 0x02 214 #define PCI_SUBCLASS_RTC 0x03 215 #define PCI_IF_GENERIC_RTC 0x00 216 #define PCI_IF_ISA_RTC 0x00 217 #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller 218 219 #define PCI_CLASS_INPUT_DEVICE 0x09 220 #define PCI_SUBCLASS_KEYBOARD 0x00 221 #define PCI_SUBCLASS_PEN 0x01 222 #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02 223 #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03 224 #define PCI_SUBCLASS_GAMEPORT 0x04 225 226 #define PCI_CLASS_DOCKING_STATION 0x0A 227 228 #define PCI_CLASS_PROCESSOR 0x0B 229 #define PCI_SUBCLASS_PROC_386 0x00 230 #define PCI_SUBCLASS_PROC_486 0x01 231 #define PCI_SUBCLASS_PROC_PENTIUM 0x02 232 #define PCI_SUBCLASS_PROC_ALPHA 0x10 233 #define PCI_SUBCLASS_PROC_POWERPC 0x20 234 #define PCI_SUBCLASS_PROC_MIPS 0x30 235 #define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor 236 237 #define PCI_CLASS_SERIAL 0x0C 238 #define PCI_CLASS_SERIAL_FIREWIRE 0x00 239 #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01 240 #define PCI_CLASS_SERIAL_SSA 0x02 241 #define PCI_CLASS_SERIAL_USB 0x03 242 #define PCI_IF_EHCI 0x20 243 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04 244 #define PCI_CLASS_SERIAL_SMB 0x05 245 246 #define PCI_CLASS_WIRELESS 0x0D 247 #define PCI_SUBCLASS_IRDA 0x00 248 #define PCI_SUBCLASS_IR 0x01 249 #define PCI_SUBCLASS_RF 0x02 250 251 #define PCI_CLASS_INTELLIGENT_IO 0x0E 252 253 #define PCI_CLASS_SATELLITE 0x0F 254 #define PCI_SUBCLASS_TV 0x01 255 #define PCI_SUBCLASS_AUDIO 0x02 256 #define PCI_SUBCLASS_VOICE 0x03 257 #define PCI_SUBCLASS_DATA 0x04 258 259 #define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller 260 #define PCI_SUBCLASS_NET_COMPUT 0x00 261 #define PCI_SUBCLASS_ENTERTAINMENT 0x10 262 263 #define PCI_CLASS_DPIO 0x11 264 265 #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c)) 266 #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s))) 267 #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p))) 268 269 #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY) 270 #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0) 271 #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1) 272 #define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0) 273 #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD) 274 #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) 275 #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE) 276 #define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0) 277 #define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0) 278 #define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0) 279 #define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0) 280 #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0) 281 #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1) 282 #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550) 283 #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB) 284 285 #define HEADER_TYPE_DEVICE 0x00 286 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01 287 #define HEADER_TYPE_CARDBUS_BRIDGE 0x02 288 289 #define HEADER_TYPE_MULTI_FUNCTION 0x80 290 #define HEADER_LAYOUT_CODE 0x7f 291 292 #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE)) 293 #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE)) 294 #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION) 295 296 #define PCI_DEVICE_ROMBAR 0x30 297 #define PCI_BRIDGE_ROMBAR 0x38 298 299 #define PCI_MAX_BAR 0x0006 300 #define PCI_MAX_CONFIG_OFFSET 0x0100 301 302 #define PCI_VENDOR_ID_OFFSET 0x00 303 #define PCI_DEVICE_ID_OFFSET 0x02 304 #define PCI_COMMAND_OFFSET 0x04 305 #define PCI_PRIMARY_STATUS_OFFSET 0x06 306 #define PCI_REVISION_ID_OFFSET 0x08 307 #define PCI_CLASSCODE_OFFSET 0x09 308 #define PCI_SUBCLASSCODE_OFFSET 0x0A 309 #define PCI_CACHELINE_SIZE_OFFSET 0x0C 310 #define PCI_LATENCY_TIMER_OFFSET 0x0D 311 #define PCI_HEADER_TYPE_OFFSET 0x0E 312 #define PCI_BIST_OFFSET 0x0F 313 #define PCI_BASE_ADDRESSREG_OFFSET 0x10 314 #define PCI_CARDBUS_CIS_OFFSET 0x28 315 #define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id 316 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C 317 #define PCI_SID_OFFSET 0x2E // SubSystem ID 318 #define PCI_SUBSYSTEM_ID_OFFSET 0x2E 319 #define PCI_EXPANSION_ROM_BASE 0x30 320 #define PCI_CAPBILITY_POINTER_OFFSET 0x34 321 #define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register 322 #define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register 323 #define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register 324 #define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register 325 326 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E 327 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E 328 329 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 330 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 331 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a 332 333 // 334 // Interrupt Line "Unknown" or "No connection" value defined for x86 based system 335 // 336 #define PCI_INT_LINE_UNKNOWN 0xFF 337 338 339 typedef struct { 340 UINT32 Reg : 8; 341 UINT32 Func : 3; 342 UINT32 Dev : 5; 343 UINT32 Bus : 8; 344 UINT32 Reserved : 7; 345 UINT32 Enable : 1; 346 } PCI_CONFIG_ACCESS_CF8; 347 348 #pragma pack() 349 350 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55 351 #define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R') 352 #define PCI_CODE_TYPE_PCAT_IMAGE 0x00 353 #define PCI_CODE_TYPE_EFI_IMAGE 0x03 354 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 355 356 #define EFI_PCI_COMMAND_IO_SPACE 0x0001 357 #define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002 358 #define EFI_PCI_COMMAND_BUS_MASTER 0x0004 359 #define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008 360 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010 361 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020 362 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040 363 #define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080 364 #define EFI_PCI_COMMAND_SERR 0x0100 365 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200 366 367 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001 368 #define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002 369 #define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004 370 #define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008 371 #define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010 372 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020 373 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040 374 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080 375 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100 376 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200 377 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400 378 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800 379 380 // 381 // Following are the PCI-CARDBUS bridge control bit 382 // 383 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080 384 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100 385 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200 386 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400 387 388 // 389 // Following are the PCI status control bit 390 // 391 #define EFI_PCI_STATUS_CAPABILITY 0x0010 392 #define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020 393 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080 394 #define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100 395 396 #define EFI_PCI_CAPABILITY_PTR 0x34 397 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14 398 399 #pragma pack(1) 400 typedef struct { 401 UINT16 Signature; // 0xaa55 402 UINT8 Reserved[0x16]; 403 UINT16 PcirOffset; 404 } PCI_EXPANSION_ROM_HEADER; 405 406 typedef struct { 407 UINT16 Signature; // 0xaa55 408 UINT8 Size512; 409 UINT8 InitEntryPoint[3]; 410 UINT8 Reserved[0x12]; 411 UINT16 PcirOffset; 412 } EFI_LEGACY_EXPANSION_ROM_HEADER; 413 414 typedef struct { 415 UINT32 Signature; // "PCIR" 416 UINT16 VendorId; 417 UINT16 DeviceId; 418 UINT16 Reserved0; 419 UINT16 Length; 420 UINT8 Revision; 421 UINT8 ClassCode[3]; 422 UINT16 ImageLength; 423 UINT16 CodeRevision; 424 UINT8 CodeType; 425 UINT8 Indicator; 426 UINT16 Reserved1; 427 } PCI_DATA_STRUCTURE; 428 429 // 430 // PCI Capability List IDs and records 431 // 432 #define EFI_PCI_CAPABILITY_ID_PMI 0x01 433 #define EFI_PCI_CAPABILITY_ID_AGP 0x02 434 #define EFI_PCI_CAPABILITY_ID_VPD 0x03 435 #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04 436 #define EFI_PCI_CAPABILITY_ID_MSI 0x05 437 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06 438 #define EFI_PCI_CAPABILITY_ID_PCIX 0x07 439 440 typedef struct { 441 UINT8 CapabilityID; 442 UINT8 NextItemPtr; 443 } EFI_PCI_CAPABILITY_HDR; 444 445 // 446 // Capability EFI_PCI_CAPABILITY_ID_PMI 447 // 448 typedef struct { 449 EFI_PCI_CAPABILITY_HDR Hdr; 450 UINT16 PMC; 451 UINT16 PMCSR; 452 UINT8 BridgeExtention; 453 UINT8 Data; 454 } EFI_PCI_CAPABILITY_PMI; 455 456 // 457 // Capability EFI_PCI_CAPABILITY_ID_AGP 458 // 459 typedef struct { 460 EFI_PCI_CAPABILITY_HDR Hdr; 461 UINT8 Rev; 462 UINT8 Reserved; 463 UINT32 Status; 464 UINT32 Command; 465 } EFI_PCI_CAPABILITY_AGP; 466 467 // 468 // Capability EFI_PCI_CAPABILITY_ID_VPD 469 // 470 typedef struct { 471 EFI_PCI_CAPABILITY_HDR Hdr; 472 UINT16 AddrReg; 473 UINT32 DataReg; 474 } EFI_PCI_CAPABILITY_VPD; 475 476 // 477 // Capability EFI_PCI_CAPABILITY_ID_SLOTID 478 // 479 typedef struct { 480 EFI_PCI_CAPABILITY_HDR Hdr; 481 UINT8 ExpnsSlotReg; 482 UINT8 ChassisNo; 483 } EFI_PCI_CAPABILITY_SLOTID; 484 485 // 486 // Capability EFI_PCI_CAPABILITY_ID_MSI 487 // 488 typedef struct { 489 EFI_PCI_CAPABILITY_HDR Hdr; 490 UINT16 MsgCtrlReg; 491 UINT32 MsgAddrReg; 492 UINT16 MsgDataReg; 493 } EFI_PCI_CAPABILITY_MSI32; 494 495 typedef struct { 496 EFI_PCI_CAPABILITY_HDR Hdr; 497 UINT16 MsgCtrlReg; 498 UINT32 MsgAddrRegLsdw; 499 UINT32 MsgAddrRegMsdw; 500 UINT16 MsgDataReg; 501 } EFI_PCI_CAPABILITY_MSI64; 502 503 // 504 // Capability EFI_PCI_CAPABILITY_ID_HOTPLUG 505 // 506 typedef struct { 507 EFI_PCI_CAPABILITY_HDR Hdr; 508 // 509 // not finished - fields need to go here 510 // 511 } EFI_PCI_CAPABILITY_HOTPLUG; 512 513 // 514 // Capability EFI_PCI_CAPABILITY_ID_PCIX 515 // 516 typedef struct { 517 EFI_PCI_CAPABILITY_HDR Hdr; 518 UINT16 CommandReg; 519 UINT32 StatusReg; 520 } EFI_PCI_CAPABILITY_PCIX; 521 522 typedef struct { 523 EFI_PCI_CAPABILITY_HDR Hdr; 524 UINT16 SecStatusReg; 525 UINT32 StatusReg; 526 UINT32 SplitTransCtrlRegUp; 527 UINT32 SplitTransCtrlRegDn; 528 } EFI_PCI_CAPABILITY_PCIX_BRDG; 529 530 #define DEVICE_ID_NOCARE 0xFFFF 531 532 #define PCI_ACPI_UNUSED 0 533 #define PCI_BAR_NOCHANGE 0 534 #define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFF 535 #define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFE 536 #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFD 537 #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFC 538 539 #define PCI_BAR_IDX0 0x00 540 #define PCI_BAR_IDX1 0x01 541 #define PCI_BAR_IDX2 0x02 542 #define PCI_BAR_IDX3 0x03 543 #define PCI_BAR_IDX4 0x04 544 #define PCI_BAR_IDX5 0x05 545 #define PCI_BAR_ALL 0xFF 546 547 #pragma pack() 548 549 // 550 // NOTE: The following header files are included here for 551 // compatibility consideration. 552 // 553 #include "EfiPci.h" 554 555 #endif 556