1;------------------------------------------------------------------------------
2;*
3;*   Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
4;*   This program and the accompanying materials
5;*   are licensed and made available under the terms and conditions of the BSD License
6;*   which accompanies this distribution.  The full text of the license may be found at
7;*   http://opensource.org/licenses/bsd-license.php
8;*
9;*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10;*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11;*
12;*
13;------------------------------------------------------------------------------
14
15    SECTION .rdata
16;
17; Float control word initial value:
18; all exceptions masked, double-extended-precision, round-to-nearest
19;
20mFpuControlWord: DW 0x37F
21;
22; Multimedia-extensions control word:
23; all exceptions masked, round-to-nearest, flush to zero for masked underflow
24;
25mMmxControlWord: DD 0x1F80
26
27DEFAULT REL
28SECTION .text
29
30;
31; Initializes floating point units for requirement of UEFI specification.
32;
33; This function initializes floating-point control word to 0x027F (all exceptions
34; masked,double-precision, round-to-nearest) and multimedia-extensions control word
35; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
36; for masked underflow).
37;
38global ASM_PFX(InitializeFloatingPointUnits)
39ASM_PFX(InitializeFloatingPointUnits):
40
41    ;
42    ; Initialize floating point units
43    ;
44    ; The following opcodes stand for instruction 'finit'
45    ; to be supported by some 64-bit assemblers
46    ;
47    DB      0x9B, 0xDB, 0xE3
48    fldcw   [mFpuControlWord]
49
50    ;
51    ; Set OSFXSR bit 9 in CR4
52    ;
53    mov     rax, cr4
54    or      rax, BIT9
55    mov     cr4, rax
56
57    ldmxcsr [mMmxControlWord]
58
59    ret
60
61