1 #ifndef _SDE_DRM_H_ 2 #define _SDE_DRM_H_ 3 4 #include "drm.h" 5 6 /* Total number of supported color planes */ 7 #define SDE_MAX_PLANES 4 8 9 /* Total number of parameterized detail enhancer mapping curves */ 10 #define SDE_MAX_DE_CURVES 3 11 12 /* Y/RGB and UV filter configuration */ 13 #define FILTER_EDGE_DIRECTED_2D 0x0 14 #define FILTER_CIRCULAR_2D 0x1 15 #define FILTER_SEPARABLE_1D 0x2 16 #define FILTER_BILINEAR 0x3 17 18 /* Alpha filters */ 19 #define FILTER_ALPHA_DROP_REPEAT 0x0 20 #define FILTER_ALPHA_BILINEAR 0x1 21 #define FILTER_ALPHA_2D 0x3 22 23 /* Blend filters */ 24 #define FILTER_BLEND_CIRCULAR_2D 0x0 25 #define FILTER_BLEND_SEPARABLE_1D 0x1 26 27 /* LUT configuration flags */ 28 #define SCALER_LUT_SWAP 0x1 29 #define SCALER_LUT_DIR_WR 0x2 30 #define SCALER_LUT_Y_CIR_WR 0x4 31 #define SCALER_LUT_UV_CIR_WR 0x8 32 #define SCALER_LUT_Y_SEP_WR 0x10 33 #define SCALER_LUT_UV_SEP_WR 0x20 34 35 /** 36 * Blend operations for "blend_op" property 37 * 38 * @SDE_DRM_BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 39 * @SDE_DRM_BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 40 * would appear opaque in case fg plane alpha 41 * is 0xff. 42 * @SDE_DRM_BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already 43 * has alpha pre-multiplication done. If the fg 44 * plane alpha is less than 0xff, apply 45 * modulation as well. This operation is 46 * intended on layers having alpha channel. 47 * @SDE_DRM_BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not 48 * alpha pre-multiplied. Apply 49 * pre-multiplication. If fg plane alpha is 50 * less than 0xff, apply modulation as well. 51 * @SDE_DRM_BLEND_OP_MAX: Used to track maximum blend operation 52 * possible by mdp. 53 */ 54 #define SDE_DRM_BLEND_OP_NOT_DEFINED 0 55 #define SDE_DRM_BLEND_OP_OPAQUE 1 56 #define SDE_DRM_BLEND_OP_PREMULTIPLIED 2 57 #define SDE_DRM_BLEND_OP_COVERAGE 3 58 #define SDE_DRM_BLEND_OP_MAX 4 59 60 /** 61 * Bit masks for "src_config" property 62 * construct bitmask via (1UL << SDE_DRM_<flag>) 63 */ 64 #define SDE_DRM_DEINTERLACE 0 /* Specifies interlaced input */ 65 66 /* DRM bitmasks are restricted to 0..63 */ 67 #define SDE_DRM_BITMASK_COUNT 64 68 69 /** 70 * Framebuffer modes for "fb_translation_mode" PLANE and CONNECTOR property 71 * 72 * @SDE_DRM_FB_NON_SEC: IOMMU configuration for this framebuffer mode 73 * is non-secure domain and requires 74 * both stage I and stage II translations when 75 * this buffer is accessed by the display HW. 76 * This is the default mode of all frambuffers. 77 * @SDE_DRM_FB_SEC: IOMMU configuration for this framebuffer mode 78 * is secure domain and requires 79 * both stage I and stage II translations when 80 * this buffer is accessed by the display HW. 81 * @SDE_DRM_FB_NON_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode 82 * is non-secure domain and requires 83 * only stage II translation when 84 * this buffer is accessed by the display HW. 85 * @SDE_DRM_FB_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode 86 * is secure domain and requires 87 * only stage II translation when 88 * this buffer is accessed by the display HW. 89 */ 90 91 #define SDE_DRM_FB_NON_SEC 0 92 #define SDE_DRM_FB_SEC 1 93 #define SDE_DRM_FB_NON_SEC_DIR_TRANS 2 94 #define SDE_DRM_FB_SEC_DIR_TRANS 3 95 96 /** 97 * Secure levels for "security_level" CRTC property. 98 * CRTC property which specifies what plane types 99 * can be attached to this CRTC. Plane component 100 * derives the plane type based on the FB_MODE. 101 * @ SDE_DRM_SEC_NON_SEC: Both Secure and non-secure plane types can be 102 * attached to this CRTC. This is the default state of 103 * the CRTC. 104 * @ SDE_DRM_SEC_ONLY: Only secure planes can be added to this CRTC. If a 105 * CRTC is instructed to be in this mode it follows the 106 * platform dependent restrictions. 107 */ 108 #define SDE_DRM_SEC_NON_SEC 0 109 #define SDE_DRM_SEC_ONLY 1 110 111 /** 112 * struct sde_drm_pix_ext_v1 - version 1 of pixel ext structure 113 * @num_ext_pxls_lr: Number of total horizontal pixels 114 * @num_ext_pxls_tb: Number of total vertical lines 115 * @left_ftch: Number of extra pixels to overfetch from left 116 * @right_ftch: Number of extra pixels to overfetch from right 117 * @top_ftch: Number of extra lines to overfetch from top 118 * @btm_ftch: Number of extra lines to overfetch from bottom 119 * @left_rpt: Number of extra pixels to repeat from left 120 * @right_rpt: Number of extra pixels to repeat from right 121 * @top_rpt: Number of extra lines to repeat from top 122 * @btm_rpt: Number of extra lines to repeat from bottom 123 */ 124 struct sde_drm_pix_ext_v1 { 125 /* 126 * Number of pixels ext in left, right, top and bottom direction 127 * for all color components. 128 */ 129 int32_t num_ext_pxls_lr[SDE_MAX_PLANES]; 130 int32_t num_ext_pxls_tb[SDE_MAX_PLANES]; 131 132 /* 133 * Number of pixels needs to be overfetched in left, right, top 134 * and bottom directions from source image for scaling. 135 */ 136 int32_t left_ftch[SDE_MAX_PLANES]; 137 int32_t right_ftch[SDE_MAX_PLANES]; 138 int32_t top_ftch[SDE_MAX_PLANES]; 139 int32_t btm_ftch[SDE_MAX_PLANES]; 140 /* 141 * Number of pixels needs to be repeated in left, right, top and 142 * bottom directions for scaling. 143 */ 144 int32_t left_rpt[SDE_MAX_PLANES]; 145 int32_t right_rpt[SDE_MAX_PLANES]; 146 int32_t top_rpt[SDE_MAX_PLANES]; 147 int32_t btm_rpt[SDE_MAX_PLANES]; 148 149 }; 150 151 /** 152 * struct sde_drm_scaler_v1 - version 1 of struct sde_drm_scaler 153 * @lr: Pixel extension settings for left/right 154 * @tb: Pixel extension settings for top/botton 155 * @init_phase_x: Initial scaler phase values for x 156 * @phase_step_x: Phase step values for x 157 * @init_phase_y: Initial scaler phase values for y 158 * @phase_step_y: Phase step values for y 159 * @horz_filter: Horizontal filter array 160 * @vert_filter: Vertical filter array 161 */ 162 struct sde_drm_scaler_v1 { 163 /* 164 * Pix ext settings 165 */ 166 struct sde_drm_pix_ext_v1 pe; 167 /* 168 * Phase settings 169 */ 170 int32_t init_phase_x[SDE_MAX_PLANES]; 171 int32_t phase_step_x[SDE_MAX_PLANES]; 172 int32_t init_phase_y[SDE_MAX_PLANES]; 173 int32_t phase_step_y[SDE_MAX_PLANES]; 174 175 /* 176 * Filter type to be used for scaling in horizontal and vertical 177 * directions 178 */ 179 uint32_t horz_filter[SDE_MAX_PLANES]; 180 uint32_t vert_filter[SDE_MAX_PLANES]; 181 }; 182 183 /** 184 * struct sde_drm_de_v1 - version 1 of detail enhancer structure 185 * @enable: Enables/disables detail enhancer 186 * @sharpen_level1: Sharpening strength for noise 187 * @sharpen_level2: Sharpening strength for context 188 * @clip: Clip coefficient 189 * @limit: Detail enhancer limit factor 190 * @thr_quiet: Quite zone threshold 191 * @thr_dieout: Die-out zone threshold 192 * @thr_low: Linear zone left threshold 193 * @thr_high: Linear zone right threshold 194 * @prec_shift: Detail enhancer precision 195 * @adjust_a: Mapping curves A coefficients 196 * @adjust_b: Mapping curves B coefficients 197 * @adjust_c: Mapping curves C coefficients 198 */ 199 struct sde_drm_de_v1 { 200 uint32_t enable; 201 int16_t sharpen_level1; 202 int16_t sharpen_level2; 203 uint16_t clip; 204 uint16_t limit; 205 uint16_t thr_quiet; 206 uint16_t thr_dieout; 207 uint16_t thr_low; 208 uint16_t thr_high; 209 uint16_t prec_shift; 210 int16_t adjust_a[SDE_MAX_DE_CURVES]; 211 int16_t adjust_b[SDE_MAX_DE_CURVES]; 212 int16_t adjust_c[SDE_MAX_DE_CURVES]; 213 }; 214 215 /* 216 * Scaler configuration flags 217 */ 218 219 /* Disable dynamic expansion */ 220 #define SDE_DYN_EXP_DISABLE 0x1 221 222 #define SDE_DRM_QSEED3LITE 223 #define SDE_DRM_QSEED4 224 225 /** 226 * struct sde_drm_scaler_v2 - version 2 of struct sde_drm_scaler 227 * @enable: Scaler enable 228 * @dir_en: Detail enhancer enable 229 * @pe: Pixel extension settings 230 * @horz_decimate: Horizontal decimation factor 231 * @vert_decimate: Vertical decimation factor 232 * @init_phase_x: Initial scaler phase values for x 233 * @phase_step_x: Phase step values for x 234 * @init_phase_y: Initial scaler phase values for y 235 * @phase_step_y: Phase step values for y 236 * @preload_x: Horizontal preload value 237 * @preload_y: Vertical preload value 238 * @src_width: Source width 239 * @src_height: Source height 240 * @dst_width: Destination width 241 * @dst_height: Destination height 242 * @y_rgb_filter_cfg: Y/RGB plane filter configuration 243 * @uv_filter_cfg: UV plane filter configuration 244 * @alpha_filter_cfg: Alpha filter configuration 245 * @blend_cfg: Selection of blend coefficients 246 * @lut_flag: LUT configuration flags 247 * @dir_lut_idx: 2d 4x4 LUT index 248 * @y_rgb_cir_lut_idx: Y/RGB circular LUT index 249 * @uv_cir_lut_idx: UV circular LUT index 250 * @y_rgb_sep_lut_idx: Y/RGB separable LUT index 251 * @uv_sep_lut_idx: UV separable LUT index 252 * @de: Detail enhancer settings 253 * @dir_weight: Directional Weight 254 * @unsharp_mask_blend: Unsharp Blend Filter Ratio 255 * @de_blend: Ratio of two unsharp mask filters 256 * @flags: Scaler configuration flags 257 */ 258 struct sde_drm_scaler_v2 { 259 /* 260 * General definitions 261 */ 262 uint32_t enable; 263 uint32_t dir_en; 264 265 /* 266 * Pix ext settings 267 */ 268 struct sde_drm_pix_ext_v1 pe; 269 270 /* 271 * Decimation settings 272 */ 273 uint32_t horz_decimate; 274 uint32_t vert_decimate; 275 276 /* 277 * Phase settings 278 */ 279 int32_t init_phase_x[SDE_MAX_PLANES]; 280 int32_t phase_step_x[SDE_MAX_PLANES]; 281 int32_t init_phase_y[SDE_MAX_PLANES]; 282 int32_t phase_step_y[SDE_MAX_PLANES]; 283 284 uint32_t preload_x[SDE_MAX_PLANES]; 285 uint32_t preload_y[SDE_MAX_PLANES]; 286 uint32_t src_width[SDE_MAX_PLANES]; 287 uint32_t src_height[SDE_MAX_PLANES]; 288 289 uint32_t dst_width; 290 uint32_t dst_height; 291 292 uint32_t y_rgb_filter_cfg; 293 uint32_t uv_filter_cfg; 294 uint32_t alpha_filter_cfg; 295 uint32_t blend_cfg; 296 297 uint32_t lut_flag; 298 uint32_t dir_lut_idx; 299 300 /* for Y(RGB) and UV planes*/ 301 uint32_t y_rgb_cir_lut_idx; 302 uint32_t uv_cir_lut_idx; 303 uint32_t y_rgb_sep_lut_idx; 304 uint32_t uv_sep_lut_idx; 305 306 /* 307 * Detail enhancer settings 308 */ 309 struct sde_drm_de_v1 de; 310 uint32_t dir_weight; 311 uint32_t unsharp_mask_blend; 312 uint32_t de_blend; 313 uint32_t flags; 314 }; 315 316 /* Number of dest scalers supported */ 317 #define SDE_MAX_DS_COUNT 2 318 319 /* 320 * Destination scaler flag config 321 */ 322 #define SDE_DRM_DESTSCALER_ENABLE 0x1 323 #define SDE_DRM_DESTSCALER_SCALE_UPDATE 0x2 324 #define SDE_DRM_DESTSCALER_ENHANCER_UPDATE 0x4 325 #define SDE_DRM_DESTSCALER_PU_ENABLE 0x8 326 327 /** 328 * struct sde_drm_dest_scaler_cfg - destination scaler config structure 329 * @flags: Flag to switch between mode for destination scaler 330 * refer to destination scaler flag config 331 * @index: Destination scaler selection index 332 * @lm_width: Layer mixer width configuration 333 * @lm_height: Layer mixer height configuration 334 * @scaler_cfg: The scaling parameters for all the mode except disable 335 * Userspace pointer to struct sde_drm_scaler_v2 336 */ 337 struct sde_drm_dest_scaler_cfg { 338 uint32_t flags; 339 uint32_t index; 340 uint32_t lm_width; 341 uint32_t lm_height; 342 uint64_t scaler_cfg; 343 }; 344 345 /** 346 * struct sde_drm_dest_scaler_data - destination scaler data struct 347 * @num_dest_scaler: Number of dest scalers to be configured 348 * @ds_cfg: Destination scaler block configuration 349 */ 350 struct sde_drm_dest_scaler_data { 351 uint32_t num_dest_scaler; 352 struct sde_drm_dest_scaler_cfg ds_cfg[SDE_MAX_DS_COUNT]; 353 }; 354 355 /* 356 * Define constants for struct sde_drm_csc 357 */ 358 #define SDE_CSC_MATRIX_COEFF_SIZE 9 359 #define SDE_CSC_CLAMP_SIZE 6 360 #define SDE_CSC_BIAS_SIZE 3 361 362 /** 363 * struct sde_drm_csc_v1 - version 1 of struct sde_drm_csc 364 * @ctm_coeff: Matrix coefficients, in S31.32 format 365 * @pre_bias: Pre-bias array values 366 * @post_bias: Post-bias array values 367 * @pre_clamp: Pre-clamp array values 368 * @post_clamp: Post-clamp array values 369 */ 370 struct sde_drm_csc_v1 { 371 int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE]; 372 uint32_t pre_bias[SDE_CSC_BIAS_SIZE]; 373 uint32_t post_bias[SDE_CSC_BIAS_SIZE]; 374 uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE]; 375 uint32_t post_clamp[SDE_CSC_CLAMP_SIZE]; 376 }; 377 378 /** 379 * struct sde_drm_color - struct to store the color and alpha values 380 * @color_0: Color 0 value 381 * @color_1: Color 1 value 382 * @color_2: Color 2 value 383 * @color_3: Color 3 value 384 */ 385 struct sde_drm_color { 386 uint32_t color_0; 387 uint32_t color_1; 388 uint32_t color_2; 389 uint32_t color_3; 390 }; 391 392 /* Total number of supported dim layers */ 393 #define SDE_MAX_DIM_LAYERS 7 394 395 /* SDE_DRM_DIM_LAYER_CONFIG_FLAG - flags for Dim Layer */ 396 /* Color fill inside of the rect, including border */ 397 #define SDE_DRM_DIM_LAYER_INCLUSIVE 0x1 398 /* Color fill outside of the rect, excluding border */ 399 #define SDE_DRM_DIM_LAYER_EXCLUSIVE 0x2 400 401 /** 402 * struct sde_drm_dim_layer - dim layer cfg struct 403 * @flags: Refer SDE_DRM_DIM_LAYER_CONFIG_FLAG for possible values 404 * @stage: Blending stage of the dim layer 405 * @color_fill: Color fill for dim layer 406 * @rect: Dim layer coordinates 407 */ 408 struct sde_drm_dim_layer_cfg { 409 uint32_t flags; 410 uint32_t stage; 411 struct sde_drm_color color_fill; 412 struct drm_clip_rect rect; 413 }; 414 415 /** 416 * struct sde_drm_dim_layer_v1 - version 1 of dim layer struct 417 * @num_layers: Numer of Dim Layers 418 * @layer: Dim layer user cfgs ptr for the num_layers 419 */ 420 struct sde_drm_dim_layer_v1 { 421 uint32_t num_layers; 422 struct sde_drm_dim_layer_cfg layer_cfg[SDE_MAX_DIM_LAYERS]; 423 }; 424 425 /* Writeback Config version definition */ 426 #define SDE_DRM_WB_CFG 0x1 427 428 /* SDE_DRM_WB_CONFIG_FLAGS - Writeback configuration flags */ 429 #define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1<<0) 430 431 /** 432 * struct sde_drm_wb_cfg - Writeback configuration structure 433 * @flags: see DRM_MSM_WB_CONFIG_FLAGS 434 * @connector_id: writeback connector identifier 435 * @count_modes: Count of modes in modes_ptr 436 * @modes: Pointer to struct drm_mode_modeinfo 437 */ 438 struct sde_drm_wb_cfg { 439 uint32_t flags; 440 uint32_t connector_id; 441 uint32_t count_modes; 442 uint64_t modes; 443 }; 444 445 #define SDE_MAX_ROI_V1 4 446 447 /** 448 * struct sde_drm_roi_v1 - list of regions of interest for a drm object 449 * @num_rects: number of valid rectangles in the roi array 450 * @roi: list of roi rectangles 451 */ 452 struct sde_drm_roi_v1 { 453 uint32_t num_rects; 454 struct drm_clip_rect roi[SDE_MAX_ROI_V1]; 455 }; 456 457 /** 458 * Define extended power modes supported by the SDE connectors. 459 */ 460 #define SDE_MODE_DPMS_ON 0 461 #define SDE_MODE_DPMS_LP1 1 462 #define SDE_MODE_DPMS_LP2 2 463 #define SDE_MODE_DPMS_STANDBY 3 464 #define SDE_MODE_DPMS_SUSPEND 4 465 #define SDE_MODE_DPMS_OFF 5 466 467 /** 468 * sde recovery events for notifying client 469 */ 470 #define SDE_RECOVERY_SUCCESS 0 471 #define SDE_RECOVERY_CAPTURE 1 472 #define SDE_RECOVERY_HARD_RESET 2 473 474 #endif /* _SDE_DRM_H_ */ 475